Llm for soc security: A paradigm shift
As the ubiquity and complexity of system-on-chip (SoC) designs increase across electronic
devices, incorporating security into an SoC design flow poses significant challenges …
devices, incorporating security into an SoC design flow poses significant challenges …
Divas: An llm-based end-to-end framework for soc security analysis and policy-based protection
Securing critical assets in a bus-based System-On-Chip (SoC) is imperative to mitigate
potential vulnerabilities and prevent unauthorized access, ensuring the integrity, availability …
potential vulnerabilities and prevent unauthorized access, ensuring the integrity, availability …
Unlocking hardware security assurance: The potential of llms
System-on-Chips (SoCs) form the crux of modern computing systems. SoCs enable high-
level integration through the utilization of multiple Intellectual Property (IP) cores. However …
level integration through the utilization of multiple Intellectual Property (IP) cores. However …
Llm-assisted generation of hardware assertions
The security of computer systems typically relies on a hardware root of trust. As
vulnerabilities in hardware can have severe implications on a system, there is a need for …
vulnerabilities in hardware can have severe implications on a system, there is a need for …
(Security) Assertions by Large Language Models
The security of computer systems typically relies on a hardware root of trust. As
vulnerabilities in hardware can have severe implications on a system, there is a need for …
vulnerabilities in hardware can have severe implications on a system, there is a need for …
Qif-verilog: Quantitative information-flow based hardware description languages for pre-silicon security assessment
Hardware vulnerabilities are often due to design mistakes because the designer does not
sufficiently consider potential security vulnerabilities at the design stage. As a result, various …
sufficiently consider potential security vulnerabilities at the design stage. As a result, various …
Analyzing security vulnerabilities induced by high-level synthesis
High-level synthesis (HLS) is essential to map the high-level language (HLL) description
(eg, in C/C++) of hardware design to the corresponding Register Transfer Level (RTL) to …
(eg, in C/C++) of hardware design to the corresponding Register Transfer Level (RTL) to …
Software/hardware co-design for llm and its application for design verification
The widespread adoption of Large Language Models (LLMs) is impeded by their
demanding compute and memory resources. The first task of this paper is to explore …
demanding compute and memory resources. The first task of this paper is to explore …
TaintFuzzer: SoC security verification using taint inference-enabled fuzzing
Modern System-on-Chip (SoC) designs containing sensitive information have become
targets of malicious attacks. Unfortunately, current verification practices still undermine the …
targets of malicious attacks. Unfortunately, current verification practices still undermine the …
Soc security verification using property checking
Security of a system-on-chip (SoC) can be weakened by exploiting the inherent and
potential vulnerabilities of the intellectual property (IP) cores used to implement the design …
potential vulnerabilities of the intellectual property (IP) cores used to implement the design …