Adaptive voltage scaling by in-situ delay monitoring for an image processing circuit

M Wirnshofer, L Heiß, AN Kakade… - 2012 IEEE 15th …, 2012 - ieeexplore.ieee.org
The proposed voltage scheme adaptively tunes the supply voltage of digital circuits,
according to PVTA variations. By exploiting unused timing margin, produced by state-of-the …

A variation-aware adaptive voltage scaling technique based on in-situ delay monitoring

M Wirnshofer, L Heiß, G Georgakos… - … on Design and …, 2011 - ieeexplore.ieee.org
In this paper, we present an adaptive voltage scaling (AVS) scheme to tune the supply
voltage of digital circuits according to variations. Compared to worst-case designs, which …

[图书][B] Variation-aware adaptive voltage scaling for digital CMOS circuits

M Wirnshofer - 2013 - books.google.com
Increasing performance demands in integrated circuits, together with limited energy
budgets, force IC designers to find new ways of saving power. One innovative way is the …

ON-LINE SUPPLY VOLTAGE SCALING BASED ON IN SITU DELAY MONITORING TO ADAPT FOR PVTA VARIATIONS

M Wirnshofer, NP Aryan, L Heiss… - Journal of Circuits …, 2012 - World Scientific
The presented Pre-Error Adaptive Voltage Scaling (AVS) approach tunes the supply voltage
of digital circuits dependent on the present Process, Voltage and Temperature variations as …

An energy-efficient supply voltage scheme using in-situ pre-error detection for on-the-fly voltage adaptation to PVT variations

M Wirnshofer, L Heiß, G Georgakos… - 2011 International …, 2011 - ieeexplore.ieee.org
The presented Pre-Error voltage scheme dynamically tunes the supply voltage of digital
circuits, according to PVT variations. By exploiting unused timing margin, produced by state …

Dynamic V/sub TH/scaling scheme for active leakage power reduction

CH Kim, K Roy - … 2002 Design, Automation and Test in Europe …, 2002 - ieeexplore.ieee.org
We present a Dynamic V/sub TH/Scaling (DVTS) scheme to save the leakage power during
active mode of the circuit. The power saving strategy of DVTS is similar to that of the …

A power-efficient pulse-based in-situ timing error predictor for PVT-variation sensitive circuits

LY Chiou, CR Huang, MH Wu - 2014 IEEE International …, 2014 - ieeexplore.ieee.org
Adaptive design is one of the most promising approaches for mitigating the large design
margin used by dynamically scaling the supply voltage and frequency of integrated circuits …

Expression of Concern: Supply Voltage Adaptive Low-Power Circuit Design

S Kirolos, Y Massoud - 2006 IEEE Dallas/CAS Workshop on …, 2006 - ieeexplore.ieee.org
In this paper, we present a circuit design that is capable of responding to changes in the
power supply voltage and adjust the gate size-ratio accordingly for minimum energy …

Built-in proactive tuning system for circuit aging resilience

N Shah, R Samanta, M Zhang, J Hu… - … Symposium on Defect …, 2008 - ieeexplore.ieee.org
VLSI circuits in nanometer VLSI technology experience significant aging effects, which are
embodied by performance degradation over operation time. Although this degradation can …

Razor: A low-power pipeline based on circuit-level timing speculation

D Ernst, NS Kim, S Das, S Pant, R Rao… - … . 36th Annual IEEE …, 2003 - ieeexplore.ieee.org
With increasing clock frequencies and silicon integration, power aware computing has
become a critical concern in the design of embedded processors and systems-on-chip. One …