[引用][C] Design of A Low-Power Cryptographic Accelerator Under Advanced Encryption Standard

P Wang, W Guan, L Liang - Journal of Circuits, Systems and …, 2024 - World Scientific
Advanced encryption standard (AES) has been a prevalent cryptographic structure in the
world. Existing AES-related cryptographic accelerators generally face the problem of high …

Design of AES architecture with area and speed tradeoff

N Shaji, PL Bonifus - Procedia Technology, 2016 - Elsevier
AES, is the well-accepted cryptographic algorithm which could be utilized to ensure security
of electronic information since it is proven to be resistive to most of the attacks. In this work …

High-throughput low-area design of AES using constant binary matrix-vector multiplication

H Lee, Y Paik, J Jun, Y Han, SW Kim - Microprocessors and Microsystems, 2016 - Elsevier
In spite of many outstanding studies, the hardware implementation of Advanced Encryption
Standard (AES) algorithm is still challenging because of recurrent computations in Galois …

A highly efficient FPGA implementation of AES for high throughput IoT applications

SS Dhanda, B Singh, P Jindal… - Journal of Discrete …, 2022 - Taylor & Francis
With nearly 500 billion connected devices in 2025, information security will be the main
concern of the researchers. It is the driving force in developing resource efficient …

[PDF][PDF] S-Box Absorption Design for Key-specific AES circuits

S Matsuoka, N Fujieda, S Ichikawa - IEEE TENCON-2014 …, 2014 - researchmap.jp
A key-specific AES (Advanced Encryption Standard) has been studied to reduce the amount
of hardware and the power consumption, where the key expansion logic and the …

A new ASIC implementation of an advanced encryption standard (AES) crypto-hardware accelerator

N Ahmad, SMR Hasan - Microelectronics Journal, 2021 - Elsevier
Single-chip hardware implementation of Advanced Encryption Standard (AES) offers a low-
power and low-area design that is suitable for portable devices. It is widely applicable for …

[PDF][PDF] A novel FPGA implementation of AES-128 using reduced residue of prime numbers based S-Box

MH Rais, SM Qasim - International Journal of Computer Science and …, 2009 - academia.edu
In this paper, we present a novel Field Programmable Gate Array (FPGA) implementation of
advanced encryption standard (AES-128) algorithm based on the design of high …

Lightweight and low-latency AES accelerator using shared SRAM

JS Lee, P Choi, DK Kim - IEEE Access, 2022 - ieeexplore.ieee.org
In this study, we propose a lightweight and low-latency advanced encryption standard (AES)
accelerator. Instead of being connected to the bus through its own slave wrapper, the …

AES-32: An FPGA implementation of lightweight-AES for IoT Devices

S Singh Dhanda, B Singh… - International Journal of …, 2023 - journal.uob.edu.bh
IoT is marked by the resource-constrained devices. Information security is the main
challenge that arise due to wireless transmission of data by ubiquitous sensors. The …

Area-power and Energy Efficient Substitution box (S-box) in Advanced Encryption Standard (AES)

O Bazgir, S Gali, T Nikoubin - … of the Great Lakes Symposium on VLSI …, 2024 - dl.acm.org
Advanced Encryption Standard (AES) is a widely used Symmetric-key algorithm. A small
characteristics improvement of AES circuits can significantly affect the system's …