Many future shared-memory multiprocessor servers will both target commercial workloads
and use highly-integrated" glueless" designs. Implementing low-latency cache coherence in …

Snooping and directory-based coherence protocols have become the de facto standard in
chip multi-processors, but neither design is without drawbacks. Snooping protocols are not …

This paper introduces dynamic self-invalidation (DSI), a new technique for reducing cache
coherence overhead in shared-memory multiprocessors. DSI eliminates invalidation …

To make shared-memory multiprocessors scalable, researchers are now exploring cache
coherence protocols that do not rely on broadcast, but instead send invalidation messages …

Write-invalidate and write-broadcast coherency protocols have been criticized for being
unable to achieve good bus performance across all cache configurations. In particular, write …

Due to data spreading among processors and due to the cache coherence problem, private
data caches have not been as effective in reducing the average memory delay in …

This paper explores a new technique called coherence decoupling, which breaks a
traditional cache coherence protocol into two protocols: a Speculative Cache Lookup (SCL) …

For constnicting large-scale shared-memory multi-processors, researchers are currently
exploring cache coherence protocols that do not rely on broadcast, but instead send …

Improvements in semiconductor technology now enable chip multiprocessors (CMPs). As
many future computer systems will use one or more CMPs and support shared memory …

Many modern computer systems and most multicore chips (chip multiprocessors) support
shared memory in hardware. In a shared memory system, each of the processor cores may …