Design and analysis of 8-bit ripple Carry Adder using nine Transistor Full Adder

GR Padmini, O Rajesh, K Raghu… - 2021 7th …, 2021 - ieeexplore.ieee.org
This paper uses a nine-transistor full adder model to design an eight-bit ripple carry adder
for less power consumption. The conventional full adder design consists of 28 transistors …

Design and analysis of a novel low-power and energy-efficient 18T hybrid full adder

M Amini-Valashani, M Ayat, S Mirzakuchaki - Microelectronics journal, 2018 - Elsevier
A novel full-swing, low-power and energy-aware full adder using hybrid logic scheme is
presented in this paper. At first, a new energy-efficient 10T XOR-XNOR cell is designed by …

Performance comparison of 1-bit conventional and hybrid full adder circuits

I Hussain, S Chaudhury - … Devices and Networking: Proceedings of ICCDN …, 2018 - Springer
Adders are the integral part of arithmetic logic units in digital system. Performance of the
adder circuits decides the performance of those circuit and systems. Full adders are …

[PDF][PDF] Comparative analysis of different types of full adder circuits

MB Damle, SS Limaye, MG Sonwani - IOSR Journal of Computer …, 2013 - academia.edu
The Full Adder circuit is an important component in application such as Digital Signal
Processing (DSP) architecture, microprocessor, and microcontroller and data processing …

Comparative Analysis of 8-Bit Manchester Carry Chain Adder Using FinFET at 18nm Technology

RR Vallabhuni, A Karthik, CHVS Kumar… - 2020 3rd …, 2020 - ieeexplore.ieee.org
Designers primary goal is to develop the Adder cell with improved performance viz. speed,
fixed rise and fall time, as it the fundamental block in VLSI design process. The dynamic …

Low power high speed 1-bit full adder circuit design at 45nm CMOS technology

AK Yadav, BP Shrivatava… - … Conference on Recent …, 2017 - ieeexplore.ieee.org
One bit full adder cell is one of the most frequently used digital circuit component in
arithmetic logic unit (ALU) and it is the essential functional unit of all computational circuit …

Analysis of different Adders using CMOS, CPL and DPL logic

S Nagaraj, GMS Reddy… - 2017 14th IEEE India …, 2017 - ieeexplore.ieee.org
In this paper we design and analyse different types of adders using CMOS, Complementary
Pass Transistor Logic (CPL), Double Pass Transistor Logic (DPL) logics. Ripple Carry …

[PDF][PDF] Low power full adder with reduced transistor count

MG Priya, K Baskaran - International Journal of Engineering …, 2013 - researchgate.net
Basic building blocks of most of the arithmetic and logic circuits are formed by XOR logic
gate. This paper proposes a new 3T-XOR gate with significant area and power savings. In …

[PDF][PDF] Two new low power high performance full adders with minimum gates

M Hosseinghadiry, H Mohammadi… - International Journal of …, 2009 - Citeseer
with increasing circuits' complexity and demand to use portable devices, power consumption
is one of the most important parameters these days. Full adders are the basic block of many …

8-Bit Carry Look Ahead Adder Using MGDI Technique

PA Babu, VS Nagaraju, RR Vallabhuni - IoT and Analytics for Sensor …, 2022 - Springer
High-performance and low power consumption are major factors that describe the
significance of a design in VLSI. At low and ultra-low power applications, power …