Reducing the delay of backend interconnects is critical in delivering improved performance
in next generation computer chips. One option is to implement interlayer dielectric (ILD) …

▪ Abstract As integrated circuit (IC) dimensions continue to decrease, RC delay, crosstalk
noise, and power dissipation of the interconnect structure become limiting factors for ultra …

As integrated circuit dimensions continue to decrease, RC delay, crosstalk noise and power
dissipation of the interconnect structure become limiting factors for ultra-large-scale …

The implementation of materials in device interconnect structure is being driven by shrinking
device geometries. In order to meet customer demands for increasing electrical …

The drive toward increased semiconductor device densities and improved performance has
set in motion the search for low-dielectric-constant materials. While introducing porosity in …

Materials with a low dielectric constant are required as interlayer dielectrics for the on-chip
interconnection of ultra-large-scale integration devices to provide high speed, low dynamic …

Abstract The International Technology Roadmap for Semiconductors predicts that continued
scaling of devices will require ultra-low-k materials with k values less than 2.5 for the 100 nm …

The fabrication of future interconnects in integrated circuits requires insulators with
decreasing dielectric constants in order to maintain or improve the electrical performance of …

With the rapid development of ultra-large-scale integration (ULSI) of integrated circuits, the
feature size of the silicon chip continues shrinking and the physical gate length is …

Future high performance on-chip interconnect requires ultra-low K materials with an effective
dielectric constant less than 2.0. Ultra-low K materials normally contain a certain degree of …