Design-for-Testability and Its Impact on Logic Locking

K Zamiri Azar, H Mardani Kamali, F Farahmandi… - Understanding Logic …, 2023 - Springer
The availability of access to integrated circuits' scan chain is an inevitable requirement of
modern ICs for testability/debugging purposes. However, leaving open access to the scan …

From cryptography to logic locking: A survey on the architecture evolution of secure scan chains

KZ Azar, HM Kamali, H Homayoun, A Sasan - IEEE Access, 2021 - ieeexplore.ieee.org
The availability of access to Integrated Circuits' scan chain is an inevitable requirement of
modern ICs for testability/debugging purposes. However, leaving access to the scan chain …

Secure and robust key-trapped design-for-security architecture for protecting obfuscated logic

HM Kamali - Cryptology ePrint Archive, 2022 - eprint.iacr.org
Having access to the scan chain of Integrated Circuits (ICs) is an integral requirement of the
debug/testability process within the supply chain. However, the access to the scan chain …

Is robust design-for-security robust enough? Attack on locked circuits with restricted scan chain access

N Limaye, A Sengupta, M Nabeel… - 2019 IEEE/ACM …, 2019 - ieeexplore.ieee.org
The security of logic locking has been called into question by various attacks, especially a
Boolean satisfiability (SAT) based attack, that exploits scan access in a working chip. Among …

Reducing logic locking key leakage through the scan chain

K Juretus, I Savidis - 2020 IEEE International Symposium on …, 2020 - ieeexplore.ieee.org
A novel technique to secure the scan chain of an integrated circuit (IC) is proposed. The
technique creates a logical partition between the functional and test modes of a circuit …

A secure scan architecture using parallel latch-based lock

W Wang, J Liang, X Wang, X Pan, S Cai - Integration, 2023 - Elsevier
In this paper, we propose a new logic locking scheme to overcome scan-based side-
channel attacks. The scheme is implemented using parallel latches and a key that includes …

Security assessment of dynamically obfuscated scan chain against oracle-guided attacks

MS Rahman, A Nahiyan, F Rahman, S Fazzari… - ACM Transactions on …, 2021 - dl.acm.org
Logic locking has emerged as a promising solution to protect integrated circuits against
piracy and tampering. However, the security provided by existing logic locking techniques is …

[PDF][PDF] SKG-Lock+: A Provably Secure Logic Locking Scheme Creating Significant Output Corruption. Electronics 2022, 11, 3906

QL Nguyen, S Dupuis, ML Flottes, B Rouzeyre - 2022 - academia.edu
The current trend to globalize the supply chain in the Integrated Circuits (ICs) industry has
raised several security concerns including, among others, IC overproduction. Over the past …

On designing secure and robust scan chain for protecting obfuscated logic

HM Kamali, KZ Azar, H Homayoun, A Sasan - arXiv preprint arXiv …, 2020 - arxiv.org
In this paper, we assess the security and testability of the state-of-the-art design-for-security
(DFS) architectures in the presence of scan-chain locking/obfuscation, a group of solution …

SKG-Lock+: A provably secure logic locking SchemeCreating significant output corruption

QL Nguyen, S Dupuis, ML Flottes, B Rouzeyre - Electronics, 2022 - mdpi.com
The current trend to globalize the supply chain in the Integrated Circuits (ICs) industry has
raised several security concerns including, among others, IC overproduction. Over the past …