Semiconductor device dimensions have been decreasing steadily over the past several
decades, generating the need to overcome fundamental limitations of both the materials …

[en] Simulation of etching and deposition processes as well as three-dimensional geometry
generation are important issues in state of the art TCAD applications. Three-dimensional …

This letter introduces an analytical model to represent line-edge roughness (LER) effects on
both off-state leakage and drive current for sub-100-nm devices. The model partitions a …

Current advanced transistor architectures, such as FinFETs and (stacked) nanowires and
nanosheets, employ truly three-dimensional architectures. Already for aggressively scaled …

The semiconductor industry will soon be launching 32 nm complementary metal oxide
semiconductor (CMOS) technology node using 193 nm lithography patterning technology to …

CMOS device patterning for aggressively scaled pitches (smaller than 80nm pitch) faces
many challenges. Maybe one of the most crucial issues during device formation is the …

Front end process simulation is an invaluable tool in assessing current and future process
options. This review describes the application of process simulation in modeling geometry …

As lithography process nodes shrink to sub-wavelength levels generating acceptable layout
patterns becomes a challenging problem. Traditionally, complex convolution based …

Semiconductor logic and memory technology development continues to push the limits of
process complexity and cost, especially as the industry migrates to the 5 nm node and …

To overcome the prohibitive barriers of edge-placement errors (EPE) in the cut/block/via step
of complementary lithography, we propose a modular patterning approach by combining …