A new adaptive selection strategy for reducing latency in networks on chip

M Trik, H Akhavan, AM Bidgoli, AMNG Molk, H Vashani… - Integration, 2023 - Elsevier
Networks on chips (NoCs) are a concept inspired by computer networks for constructing
multiprocessor systems that can handle communication across processing cores. One of the …

A hybrid selection strategy based on traffic analysis for improving performance in networks on chip

M Trik, AMNG Molk, F Ghasemi… - Journal of …, 2022 - Wiley Online Library
Networks on chip (NoCs) are an idea for implementing multiprocessor systems that have
been able to handle the communication between processing cores, inspired by computer …

Improving routing efficiency for network-on-chip through contention-aware input selection

D Wu, BM Al-Hashimi, MT Schmitz - Proceedings of the 2006 Asia and …, 2006 - dl.acm.org
The performance of Network-on-Chip (NoC) largely depends on the underlying routing
techniques, which have two constituencies: output selection and input selection. Previous …

Q-learning based congestion-aware routing algorithm for on-chip network

F Farahnakian, M Ebrahimi… - 2011 IEEE 2nd …, 2011 - ieeexplore.ieee.org
Network congestion can limit performance of NoC due to increased transmission latency
and power consumption. Congestion-aware adaptive routing can greatly improve the …

Performance assessment of adaptive core mapping for NoC-based architectures

AS Kumar, TVKH Rao - International Journal of Embedded …, 2022 - inderscienceonline.com
In this trending technology of network-on-chip, the large number of cores embedded on-chip
had a rapid growth resulting in performance degradation. Many methodologies came into …

Aergia: Exploiting packet latency slack in on-chip networks

R Das, O Mutlu, T Moscibroda, CR Das - ACM SIGARCH computer …, 2010 - dl.acm.org
Traditional Network-on-Chips (NoCs) employ simple arbitration strategies, such as round-
robin or oldest-first, to decide which packets should be prioritized in the network. This is …

An analytical approach for network-on-chip performance analysis

UY Ogras, P Bogdan… - IEEE Transactions on …, 2010 - ieeexplore.ieee.org
Networks-on-chip (NoCs) have recently emerged as a scalable alternative to classical bus
and point-to-point architectures. To date, performance evaluation of NoC designs is largely …

Evaluation of low power consumption network on chip routing architecture

TS Arulananth, M Baskar, US SM, R Thiagarajan… - Microprocessors and …, 2021 - Elsevier
Abstract Network on Chip (NoC) is growing technology whereby multiprocessor state
interconnect patterns are formed. NoC technology is adapted to support a variety of …

Implementation and analysis of a new selection strategy for adaptive routing in networks-on-chip

G Ascia, V Catania, M Palesi… - IEEE transactions on …, 2008 - ieeexplore.ieee.org
Efficient and deadlock-free routing is critical to the performance of networks-on-chip. The
effectiveness of any adaptive routing algorithm strongly depends on the underlying selection …