Variability mitigation in nanometer CMOS integrated systems: A survey of techniques from circuits to software

A Rahimi, L Benini, RK Gupta - Proceedings of the IEEE, 2016 - ieeexplore.ieee.org
Variation in performance and power across manufactured parts and their operating
conditions is an accepted reality in modern microelectronic manufacturing processes with …

Impact of parameter variations on circuits and microarchitecture

OS Unsal, JW Tschanz, K Bowman, V De, X Vera… - Ieee …, 2006 - ieeexplore.ieee.org
Parameter variations, which are increasing along with advances in process technologies,
affect both timing and power. Variability must be considered at both the circuit and …

Error-resilient design techniques for reliable and dependable computing

S Das, DM Bull, PN Whatmough - IEEE Transactions on Device …, 2015 - ieeexplore.ieee.org
Integrated circuits in modern systems-on-chip and microprocessors are typically operated
with sufficient timing margins to mitigate the impact of rising process, voltage, and …

Improving resilience to timing errors by exposing variability effects to software in tightly-coupled processor clusters

A Rahimi, D Cesarini, A Marongiu… - IEEE Journal on …, 2014 - ieeexplore.ieee.org
Manufacturing and environmental variations cause timing errors in microelectronic
processors that are typically avoided by ultra-conservative multi-corner design margins or …

Revival: A variation-tolerant architecture using voltage interpolation and variable latency

X Liang, GY Wei, D Brooks - IEEE micro, 2009 - ieeexplore.ieee.org
Process variations will significantly degrade the performance benefits of future
microprocessors as they move toward nanoscale technology. Device parameter fluctuations …

Revival: A variation-tolerant architecture using voltage interpolation and variable latency

X Liang, GY Wei, D Brooks - ACM SIGARCH Computer Architecture …, 2008 - dl.acm.org
Process variations are poised to significantly degrade performance benefits sought by
moving to the next nanoscale technology node. Parameter fluctuations in devices can …

Error Detection and Recovery Techniques for Variation-Aware CMOS Computing: A Comprehensive Review

J Crop, E Krimer, N Moezzi-Madani… - Journal of Low Power …, 2011 - mdpi.com
While Moore's law scaling continues to double transistor density every technology
generation, new design challenges are introduced. One of these challenges is variation …

Variability in VLSI circuits: Sources and design considerations

MH Abu-Rahma, M Anis - 2007 IEEE International Symposium …, 2007 - ieeexplore.ieee.org
Process variations are becoming of increasing importance in nanometer CMOS regime. This
paper reviews the challenges associated with variability and variation-tolerant design in …

A cross-layer technology-based study of how memory errors impact system resilience

VB Kleeberger, C Gimmler-Dumont, C Weis… - IEEE Micro, 2013 - ieeexplore.ieee.org
Highly scaled technologies at and beyond the 22-nm node exhibit increased sensitivity to
various scaling-related problems that conspire to reduce the overall reliability of integrated …

VARIUS: A model of process variation and resulting timing errors for microarchitects

SR Sarangi, B Greskamp, R Teodorescu… - IEEE Transactions …, 2008 - ieeexplore.ieee.org
Within-die parameter variation poses a major challenge to high-performance
microprocessor design, negatively impacting a processor's frequency and leakage power …