A method of emulating a circuit design using an emulator is presented. The method includes
allocating one or more spare routing resources to one or more field programmable gate …

An emulation environment includes a host system and an emulator. The host system
configures the emulator to load a design under test (DUT) and the emulator emulates the …

(57) ABSTRACT A system for emulating a circuit design is presented. The system includes a
host workstation coupled by an emulation interface to a field programmable gate array …

The disclosure generally relates to the emulation of cir cuits, and more specifically to
debugging an emulated design under test (DUT). 2. Description of the Related Art Emulators …

An apparatus and method for implementing synchronous triggers for waveform capture in a
multiple FPGA system is described. The apparatus includes trigger net circuitry that has one …

(57) ABSTRACT A “complete graph'interconnect Structure for a hardware emulator for
reducing the required programmable intercon nect resource in the emulator and using the …

The interconnect pin count between field programmable gate arrays (FPGAS) used in
prototyping an application specific integrated circuit (ASIC) is reduced without compromising …

A System and method for emulating an ASIC using multiple filed programmable gate arrayS.
A designer, using this method, emulates an integrated circuit design using a pro PO Box …

A field programmable gate array (FPGA) and methods for executing operations using an
FPGA are provided. The method includes providing a first dynamic macro and a second …

US6173419B1 - Field programmable gate array (FPGA) emulator for debugging software -
Google Patents US6173419B1 - Field programmable gate array (FPGA) emulator for debugging …