Buffers in on-chip networks consume significant energy, occupy chip area, and increase
design complexity. In this paper, we make a case for a new approach to designing on-chip …

With the emergence of many-core architectures, it is quite likely that multiple applications will
run concurrently on a system. Existing locally and globally adaptive routing algorithms …

On-chip networks are critical to the scaling of future multi-core processors. The challenge for
on-chip network is to reduce the cost including power consumption and area while providing …

It is expected that future on-chip networks for many-core processors will impose huge
overheads in terms of energy, delay, complexity, verification effort, and area. There is a …

Driven by the need for higher bandwidth and complexity reduction, off-chip interconnect has
evolved from proprietary busses to networked architectures. A similar evolution is occurring …

Many of the issues that will be faced by the designers of multi-billion transistor chips may be
alleviated by the presence of a flexible global communication infrastructure. In the short …

Some current and most future systems-on-chips use and will use network
architectures/protocols to implement on-chip communication. On-chip networks borrow …

The increased deployment of System-on-Chip designs has drawn attention to the limitations
of on-chip interconnects. As a potential solution to these limitations, Networks-on-Chip …

As technology scaling drives the number of processor cores upward, current on-chip routers
consume substantial portions of chip area and power budgets. Since existing research has …

In this paper, we present and evaluate a novel routing scheme called DyAD which combines
the advantages of both deterministic and adaptive routing schemes. More precisely, we …