Low-Phase-Noise 20-GHz Phase-Locked Loop Using Harmonic-Tuned VCO Assisting With -Boosting Technique

HS Lee, TH Jang, JH Kim… - IEEE Transactions on Very …, 2023 - ieeexplore.ieee.org
In this study, we present a low-phase-noise 20-GHz phase-locked loop (PLL) with
simultaneous-boosted and third-harmonic impedance-tuned voltage-controlled oscillator …

A 990- 1.6-GHz PLL Based on a Novel Supply-Regulated Active-Loop-Filter VCO

KC Choi, SG Kim, SW Lee, BC Lee… - IEEE Transactions on …, 2013 - ieeexplore.ieee.org
A low-power 1.6-GHz phase-locked loop (PLL) based on a novel supply-regulated voltage-
controlled oscillator (SR-VCO) including an active-loop filter (ALF) is realized. In this PLL, an …

A 0.5 V 5.96-GHz PLL with amplitude-regulated current-reuse VCO

S Ikeda, S Lee, H Ito, N Ishihara… - IEEE Microwave and …, 2017 - ieeexplore.ieee.org
This letter proposes an ultralow-power 5.96-GHz phase-locked loop (PLL) with a current-
reuse VCO under low supply voltage of 0.5 V. While the current-reuse VCO can achieve …

25.6 A 70.5-to-85.5 GHz 65nm phase-locked loop with passive scaling of loop filter

Z Huang, HC Luong, B Chi, Z Wang… - 2015 IEEE International …, 2015 - ieeexplore.ieee.org
To support 16-QAM modulation in E-band applications, phase-locked loops (PLLs) are
required to have wide a frequency tuning range from 71 to 86GHz and low phase noise of …

A 24-GHz fully integrated phase-locked loop for 60-GHz beamforming

C Zhou, L Zhang, D Yang, Y Wang… - 2012 IEEE 11th …, 2012 - ieeexplore.ieee.org
A 24-GHz fully integrated integer-N phase-locked loop (PLL) is presented in this paper.
Benefiting from the bias noise filtering technique, the voltage controlled oscillator (VCO) in …

A 56-to-66 GHz quadrature phase-locked loop with a wide locking range divider chain in 65nm CMOS

B Zhou, L Zhang, Y Wang, Z Yu - 2015 IEEE International …, 2015 - ieeexplore.ieee.org
A low power and low phase noise phase-locked loop (PLL) is proposed in this paper to
provide a quadrature millimeter-wave source for the 60GHz direct-conversion transceiver …

A 5.5 GHz low-power PLL using 0.18-µm CMOS technology

JH Tsai, SW Huang, JP Chou - 2014 IEEE Radio and Wireless …, 2014 - ieeexplore.ieee.org
This paper presents a fully-integrated 5.5 GHz low-power consumption phase-locked loop
(PLL) on standard 0.18-µm CMOS process. Utilizing the transformer feedback VCO and high …

A dual-loop phase locked loop with frequency to voltage converter

X Jin, KW Kwon, YS Choi, JH Chun - Journal of Semiconductor …, 2019 - dbpia.co.kr
This paper proposes a 1.5-GHz ring oscillator-based dual-loop phase locked loop (PLL) with
a frequency-to-voltage converter (FVC). By forming an additional high bandwidth path in the …

A 1.8–6.3 ghz quadrature ring vco-based fast-settling pll for wireline i/o in 55nm cmos

JS Gaggatur - 2021 34th International Conference on VLSI …, 2021 - ieeexplore.ieee.org
A wide-operating range quadrature ring voltage controlled oscillator (VCO) based phase
locked loop (PLL) having a phase frequency detector (PFD) with dead-zone removal and …

A 1-V 24-GHz 17.5-mW phase-locked loop in a 0.18-/spl mu/m CMOS process

AWL Ng, GCT Leung, KC Kwok… - IEEE journal of solid …, 2006 - ieeexplore.ieee.org
A 1-V 24-GHz 17.5-mW fully integrated phase-locked loop employing a transformer-
feedback voltage-controlled oscillator and a stacked divide-by-2 frequency divider for low …