Effects of logic glitch and (area-power dissipation) leakage on cryptosystems using clock gating technique to enhance web etiquette

AT Ehis - Brazilian Journal of Science, 2023 - periodicos.cerradopub.com.br
The last century has seen an evolution in technology that has improved communication
systems and, in general, made life easier for people. Our communication systems have …

Mathematical model for glitch power consumption to study its implication on power analysis attacks

AS Sichani, WA Moreno - 2018 IEEE 9th Latin American …, 2018 - ieeexplore.ieee.org
Side channel information is a major threat against cryptographic circuits. Since
cryptographic algorithms are implemented on microprocessors or custom hardware, the …

[PDF][PDF] A review on glitch reduction techniques

D Vikas - Int. J. Res. Eng. Technol, 2014 - academia.edu
This paper presents different techniques for reducing glitch power in digital circuits. The aim
of this study is to minimize glitch power as glitch power comes under dynamic power, so that …

Multiple threshold voltage for glitch power reduction

M Slimani, P Matherat - 2011 Faible Tension Faible …, 2011 - ieeexplore.ieee.org
We address the problem of circuit-level design for low power. We describe a new method for
glitch power reduction based on threshold voltage adjustment. The proposed method …

Introduction of a new technique for simultaneous reduction of the delay and leakage current in digital circuits

H Mohammadian, MB Tavakolib, F Setoudeh, A Horri - Integration, 2021 - Elsevier
By the reduction in the size of transistors and the development of submicron technology, as
well as the construction of more integrated circuits on chips, leakage power has become one …

Logic design techniques for 65 to 45nm and below for reducing total energy and solving technology variations problems

D Helms, W Nebel - 2007 14th IEEE International Conference …, 2007 - ieeexplore.ieee.org
In sub-100 nm technologies, leakage related problems are based on the standby current's
exponential dependency on both, parameter scaling and parameter variation …

[PDF][PDF] A comparative study of ultra-low voltage digital circuit design

A Arthurs, J Roark, J Di - International Journal of VLSI Design & …, 2012 - academia.edu
Ultra-low voltage digital circuit design is an active research area, especially for portable
applications such as wearable electronics, intelligent remote sensors, implantable medical …

Design and calibration of a small-footprint, low-frequency, and low-power gate leakage timer using differential leakage technique

Y Nishio, A Kobayashi, K Niitsu - IEICE Transactions on Electronics, 2019 - search.ieice.org
This study proposes a design and calibration method for a small-footprint, low-frequency,
and low-power gate leakage timer using a differential leakage technique for IoT …

Analysis of low power feed through logic with leakage control technique

P Bikki, P Karuppanan - 2017 4th International Conference on …, 2017 - ieeexplore.ieee.org
In this article, novel leakage control techniques are adopted in Feed-Through Logic (FTL) for
low power high-speed designs. The FTL design has a unique feature; the outputs are …

Adaptive clock generation technique for variation-aware subthreshold logics

W Rim, W Choi, J Park - … on Circuits and Systems II: Express …, 2012 - ieeexplore.ieee.org
Subthreshold logic has become an attractive option in energy-constrained applications,
where the key metric is energy consumption rather than operating speed or silicon area …