L Minnick, PL Connor - US Patent 7,248,593, 2007 - Google Patents
A method, apparatus, and article of manufacture for retaining packet order in multiprocessor systems utilizing multiple transmit queues while minimizing spinlocks are disclosed herein …
V Aggarwal, W Boland, B McKinley… - US Patent App. 10 …, 2003 - Google Patents
The present invention provides systems for improved quality of service and traffic management in network routers and other devices. This is achieved, according to one …
LB Brenner, LM Browning - US Patent 6,986,140, 2006 - Google Patents
The invention is directed to apparatus and methods for periodic load balancing in a multiple run queue System. 2. Description of Related Art Multiple processor Systems are generally …
H Stracovsky, P Szabelski - US Patent 6,510,474, 2003 - Google Patents
the present invention pertains generally to computing systems. More specifically, the present invention relates to a providing access to shared resources in a computing system such as …
YM Chen, H Chung, Z Tong, E Lee - US Patent 6,975,638, 2005 - Google Patents
Methods and apparatus for interleaved Weighted fair data packet queue sequencing are disclosed. An interleaving table speci? es a queue sequence. A queue sequencer folloWs …
LB Brenner, LM Browning - US Patent 6,993,767, 2006 - Google Patents
An apparatus and methods for periodic load balancing in a multiple run queue system are provided. The apparatus includes a controller, memory, initial load balancing device, idle …
V Sukonik, M Laor, MB Galles, M Voloshin… - US Patent …, 2007 - Google Patents
Methods and apparatus are disclosed for processing packets, for example, using a high performance massively parallel packet processing architecture, distributing packets or …
LB Brenner - US Patent 7,065,766, 2006 - Google Patents
Apparatus and methods for load balancing fixed priority threads in a multiprocessor system are provided. The apparatus and methods of the present invention identify unbound fixed …
JG Chen, DE Clune, HZ Moller, DP Sonnier - US Patent 6,754,795, 2004 - Google Patents
A processing system comprises processing circuitry and memory circuitry coupled to the processing circuitry. The memory circuitry is configurable to maintain at least one queue …