Fault Tolerant FPGA Implementation on Redundancy Techniques and ECG Denoising

S SM - arXiv preprint arXiv:2304.08165, 2023 - arxiv.org
As more the communications and signal process we use in the today life the more we intend
to develop more reliable devices which gives fewer errors due to transient fault, So we use a …

Fault-tolerant digital filters on FPGA using hardware redundancy techniques

P Mallavarapu, HN Upadhyay… - 2017 International …, 2017 - ieeexplore.ieee.org
As the technology is growing rapidly in recent years, communication and signal processing
systems become more complex with the increase in a number of elements or devices. To …

[PDF][PDF] Overview of fault tolerance techniques and the proposed TMR generator tool for FPGA designs

AR Khatri - … Journal of Advanced Computer Science and …, 2020 - pdfs.semanticscholar.org
The FPGA has been involved in many safety and mission-critical applications in the last few
decades. FPGA designs are also critical to errors and failures due to radiations. Fault …

Real-time FPGA-based fault tolerant and recoverable technique for arithmetic design using functional triple modular redundancy (FRTMR)

SC Anjankar, AM Pund, R Junghare, J Zalke - Proceedings of the Second …, 2018 - Springer
Abstract Single Event Upset (SEU) is a serious issue when considering the real-time
process for critical time constraint applications. Scaling of the devices, in complex computing …

DMR+: An efficient alternative to TMR to protect registers in Xilinx FPGAs

P Reviriego, M Demirci, J Tabero, A Regadío… - Microelectronics …, 2016 - Elsevier
Registers are one of the circuit elements that can be affected by soft errors. To ensure that
soft errors do not affect the system functionality, Triple Modular Redundancy (TMR) is …

[PDF][PDF] Reduced Resolution Redundancy: A Novel Approximate Error Mitigation Technique

H MARTÍN - e-archivo.uc3m.es
Error mitigation techniques, such as Triple Modular Redundancy, introduce very large
overheads. To alleviate this overhead, approximate techniques can be used. In this work we …

Reduced resolution redundancy: A novel approximate error mitigation technique

LA García-Astudillo, L Entrena, A Lindoso… - IEEE Access, 2022 - ieeexplore.ieee.org
Error mitigation techniques, such as Triple Modular Redundancy, introduce very large
overheads. To alleviate this overhead, approximate techniques can be used. In this work we …

[PDF][PDF] Implementation of fault tolerant method using BCH code on FPGA

VP Mahadevaswamy, SL Sunitha… - International Journal of Soft …, 2012 - Citeseer
The Fault tolerance degradation is the property that enables a system (often computer-
based) to continue operating properly in the event of the failure of (or one or more faults …

FPGA Based Parallel Filters for Failure Recovery

R Katru, M Chandrasekher - 2019 3rd International Conference …, 2019 - ieeexplore.ieee.org
Parallel failure recovery and mean time between failures is very important for VLSI digital
electronic circuits. Different fault tolerance mechanisms are available for designing a chip …

[PDF][PDF] FPGA-based redundancy bits reduction algorithm using the enhanced error detection correction code

LKS Tolentino, MVC Padilla… - International Journal of …, 2018 - academia.edu
To ensure an error-free transmission in packet switching, additional check bits (either
header or a payload) are typically appended to the input data of a message for error …