Investigation and Analysis of Dual Metal Gate Overlap on Drain Side Tunneling Field Effect Transistor with Spacer in 10nm Node

S Howldar, B Balaji, K Srinivasa Rao - International Journal of Engineering, 2024 - ije.ir
This paper investigates the electrical behavior and performance of a Dual Metal Gate
Overlap on Drain Side Tunnel Field Effect Transistor with Spacer (DMG-ODS-TFET) in 10 …

Gate Oxide Thickness and Drain Current Variation of Dual Gate Tunnel Field Effect Transistor

S Howldar, B Balaji, K Srinivasa Rao - International Journal of Engineering, 2024 - ije.ir
Two-dimensional analytical modelling of Dual Material Gate Tunnel Field Effect Transistor
with change in variation of gate oxide thickness (DMG-UOX-TFET) is proposed in this work …

[PDF][PDF] Design and analysis of hetero dielectric dual material gate underlap spacer tunnel field effect transistor

S Howldar, B Balaji, K Srinivasa Rao - International Journal of Engineering …, 2023 - ije.ir
This paper presents a design and analysis of a Hetero Dielectric Dual Material Gate
Underlap Spacer Tunnel Field Effect Transistor, aiming to enhance device performance and …

Metal drain double-gate tunnel field effect transistor with underlap: Design and simulation

A Khan, SA Loan - Silicon, 2021 - Springer
In this paper, we propose and simulate a novel double gate tunnel field effect transistor (DG-
TFET) employing a metallic drain and a gate-drain underlap. The use of a metallic drain and …

[PDF][PDF] Design and Analysis of Symmetrical Dual Gate Tunnel Field Effect Transistor with Gate Dielectric Materials in 10nm Technology

S Buttol, B Balaji, KS Rao - International Journal of Engineering, 2024 - ije.ir
In this work, a Symmetrical Dual Gate Tunnel Field Effect Transistor (SDGTFET) is proposed
with gate dielectric materials in 10nm technology. The electrical performance parameters of …

TCAD simulations of double gate tunnel field effect transistor with spacer drain overlap base on vertical Tunneling

S Singh, SS Chauhan - 2017 International conference of …, 2017 - ieeexplore.ieee.org
Effects of the spacer-drain overlap on the performance parameters of the double gate tunnel
field effect transistor is proposed and investigated in this paper. By proper fabrication of the …

Germanium source metal drain tunnel FET with dual dielectric underlap

A Khan, HI Alkhammash, SA Loan, Fellow IETE - Silicon, 2022 - Springer
In this paper, we propose, design and simulate a new double gate (DG) tunnel field effect
transistor (TFET), using germanium (Ge) source, dual dielectric gate oxide, gate/drain …

[HTML][HTML] Analysis on tunnel field-effect transistor with asymmetric spacer

HW Kim, D Kwon - Applied Sciences, 2020 - mdpi.com
Tunnel field-effect transistor (Tunnel FET) with asymmetric spacer is proposed to obtain high
on-current and reduced inverter delay simultaneously. In order to analyze the proposed …

Impact of spacer-gate engineered Workfunction on the performance of Dopingless TFET

SS Chauhan, N Sharma - Journal of Nanoelectronics and …, 2018 - ingentaconnect.com
In this paper, an optimally designed double metal gate dopingless tunnel field effect
transistor (DMG-DLTFETs) with high dielectric material spacer is investigated. With the …

Modified gate oxide double gate tunnel field-effect transistor

P Karmakar, PK Sahu - Silicon, 2022 - Springer
This paper proposes a unique Tunnel Field-Effect Transistor (TFET) structure in which the
gate oxide is modified, and the performances of the device are analyzed using Sentaurus …