Lookaside: Augmenting the Performance of Packet Processing Pipeline

MK Khattak, H Fahim, MF Majeed… - IEEE Systems …, 2020 - ieeexplore.ieee.org
The network switches and routers need to forward the network packets at a line-rate. The
underlying hardware and software implementations may limit the performance of these …

TOSwitch: Programmable and high-throughput switch using hybrid switching chips

MK Khattak, Y Tang, US Khan - IEEE Communications Letters, 2019 - ieeexplore.ieee.org
The future of networking switches and routers foresees in two key features: Programmability
and Throughput. In this letter, we propose a Traffic Offload Switch (TOSwitch) model for such …

Tiny Tera: a packet switch core

N McKeown, M Izzard, A Mekkittikul, W Ellersick… - IEEE micro, 1997 - ieeexplore.ieee.org
Describes Tiny Tera: a small, high-bandwidth, single-stage switch. Tiny Tera has 32 ports
switching fixed-size packets, each operating at over 10 Gbps (approximately the Sonet OC …

A NOVEL FLEXIBLE ON-CHIP SWITCH ARCHITECTURE FOR RECONFIGURABLE HARDWARE ACCELERATORS

ŞE Schmidt - 2021 - open.metu.edu.tr
This thesis work proposes ReFlex Switch, a novel, scalable on-chip packet switch
architecture, that is designed to interconnect heterogeneous IP cores at high speeds. One …

A reconfigurable hardware architecture for packet processing

T DUAN, J LAN, Y HU, S LIU - Chinese Journal of Electronics, 2018 - Wiley Online Library
In this paper, we propose a reconfigurable packet processing hardware architecture for
future switch, in which several protocol‐independent action units are introduced to remove …

Technologies and building blocks for fast packet forwarding

W Bux, WE Denzel, T Engbersen… - IEEE …, 2001 - ieeexplore.ieee.org
We provide a review of the state of the art and the future of packet processing and switching.
The industry's response to the need for wire-speed packet processing devices whose …

Simplifying data path processing in next-generation routers

Q Wu, D Chasaki, T Wolf - Proceedings of the 5th ACM/IEEE Symposium …, 2009 - dl.acm.org
Customizable packet processing is an important aspect of next-generation networks. Packet
processing architectures using multi-core systems on a chip can be difficult to program. In …

Low power hardware implementations for network packet processing elements

SK Shukla - Integration, 2018 - Elsevier
The real world network packet processing demands high performance hardware to achieve
the required speed. This paper proposes the various hardware optimizations on payload …

Scalable hardware priority queue architectures for high-speed packet switches

SW Moon, J Rexford, KG Shin - IEEE Transactions on …, 2000 - ieeexplore.ieee.org
With effective packet-scheduling mechanisms, modern integrated networks can support the
diverse quality-of-service requirements of emerging applications. However, arbitrating …

[PDF][PDF] Hybrid Switch: Dynamic Flow Rule Offloading on High Performance Networking Hardware

M Härdtlein - kom.tu-darmstadt.de
Hybrid switches are a new approach of combining the flexibility of programmable switches
with the power of packet forwarding on standardized hardware. Those hybrid switches …