Fault simulation for sequential circuits numbers among the highly compute intensive tasks in
the integrated circuit design process. In the quest for rapid design turn around …

We propose a new approach to parallelizing fault simulation in which the test set is
partitioned among the available processors. The approach can be used for any of the …

We propose three synchronous parallel algorithms for scalable parallel test set partitioned
fault simulation. The algorithms are based on a new two-stage approach to parallelizing fault …

A new technique to parallelize fault simulation for combinational digital circuits, suitable for
message passing based parallel processors, is described. Speedup is achieved via …

The paper describes COMBINED, a super fast fault simulator for synchronous sequential
circuits. COMBINED results from coupling a parallel pattern simulator with a nonparallel …

Consideration is given to the use of general-purpose multiprocessors for various simulation
tasks. The aims of the work are to define a general framework for the parallel simulation of …

This paper discusses the important role of fault grouping in a parallel 32-bit fault simulator
such as PROOFS. Three algorithms are presented which dynamically order the fault list …

A highly successful parallel fault simulator, called PROOFS, for synchronous sequential
circuits has been reported. The performance of PROOFS has been substantially improved in …

The authors describe PROOFS, a fast fault simulator for synchronous sequential circuits,
PROOFS achieves high performance by combining all the advantages of differential fault …

The authors present a concurrent fault simulation algorithm. The pipelined algorithm is
suitable for implementation on memory limited hardware accelerators and message passing …