Co-relation scan attack analysis (COSAA) on AES: A comprehensive approach
Scan based DfT is indispensable for IC testing in the semiconductor chip industry to ensure
correctness of chip, both functionally and structurally. Since a higher degree of fault …
correctness of chip, both functionally and structurally. Since a higher degree of fault …
A novel differential scan attack on advanced DFT structures
Scan chains insertion is the most common technique to ensure the testability of digital cores,
providing high fault coverage. However, for ICs dealing with secret information, scan chains …
providing high fault coverage. However, for ICs dealing with secret information, scan chains …
A secure DFT architecture protecting crypto chips against scan-based attacks
W Wang, J Wang, W Wang, P Liu, S Cai - IEEE Access, 2019 - ieeexplore.ieee.org
Scan design is a widely used design-for-test methodology since it enhances the
controllability and observability of integrated circuits significantly. However, it may become a …
controllability and observability of integrated circuits significantly. However, it may become a …
Robust secure scan design against scan-based differential cryptanalysis
Scan technology carries the potential risk of being misused as a “side channel” to leak out
the secrets of crypto cores. The existing scan-based attacks could be viewed as one kind of …
the secrets of crypto cores. The existing scan-based attacks could be viewed as one kind of …
Static and dynamic obfuscations of scan data against scan-based side-channel attacks
A Cui, Y Luo, CH Chang - IEEE Transactions on Information …, 2016 - ieeexplore.ieee.org
Due to the fallibility of advanced integrated circuit (IC) fabrication processes, scan test has
been widely used by cryptographic ICs to provide high fault coverage. Full controllability and …
been widely used by cryptographic ICs to provide high fault coverage. Full controllability and …
Novel test-mode-only scan attack and countermeasure for compression-based scan architectures
Scan design is a de facto design-for-testability (DfT) technique that enhances access during
manufacturing test process. However, it can also be used as a back door to leak secret …
manufacturing test process. However, it can also be used as a back door to leak secret …
On Securing Cryptographic ICs against Scan-based Attacks: A Hamming Weight Distribution Perspective
Scan chain-based Design for Testability is the industry standard in use for testing
manufacturing defects in the semiconductor industry to ensure the structural and functional …
manufacturing defects in the semiconductor industry to ensure the structural and functional …
A novel countermeasure against differential scan attack in AES algorithm
Abstract The Design for Testability (specifically scan designs) is standard testing techniques
for Digital cores for achieving high fault coverage and to provide better controllability and …
for Digital cores for achieving high fault coverage and to provide better controllability and …
Dynamically variable secure scan architecture against scan-based side channel attack on cryptography LSIs
(in English) Scan test is a powerful and popular test technique because it can control and
observe the internal states of the circuit under test. However, scan chains would be used to …
observe the internal states of the circuit under test. However, scan chains would be used to …
AES design space exploration new line for scan attack resiliency
Crypto-chips are vulnerable to side-channel attacks. Scan attack is one such side-channel
attack which uses the scan-based DFT test infrastructure to leak the secret information of the …
attack which uses the scan-based DFT test infrastructure to leak the secret information of the …