Efficient FPGA implementation of an RFIR filter using the APC–OMS technique with WTM for high-throughput signal processing

KS Reddy, S Madhavan, P Falkowski-Gilski… - Electronics, 2022 - mdpi.com
Nowadays, Finite Impulse Response (FIR) filters are used to change the attributes of a
signal in the time or frequency domain. Among FIR filters, a reconfigurable filter has the …

[PDF][PDF] A low power VLSI implementation of reconfigurable FIR filter using carry bypass adder

KS Reddy, HN Suresh - Int. J. Intell. Eng. Syst, 2018 - academia.edu
Reconfigurable Finite Impulse Response (RFIR) filter plays an important role in Software
Defined Ratio (SDR) systems, whose filter co-efficient change dynamically during runtime. In …

A low-power vlsi implementation of rfir filter design using radix-2 algorithm with lcsla

K Satish Reddy, HN Suresh - IETE Journal of Research, 2020 - Taylor & Francis
The multimedia applications and mobile communication systems require an efficient
reconfigurable finite impulse response (RFIR) filter designs for achieving low area, power …

FPGA-Based Implementation of Reconfigurable Floating-Point FIR Digital Filter

N Zhang, X Wei, B Li, H Chen - … , and Systems: Proceedings of the 8th …, 2020 - Springer
As a critical digital signal processing method, finite impulse response (FIR) digital filter is
widely used in radar signal processing, synthetic aperture radar (SAR) signal processing …

Shift add approach based implementation of RNS-FIR filter using modified product encoder

KS Reddy, S Bajaj, SS Kumar - TENCON 2014-2014 IEEE …, 2014 - ieeexplore.ieee.org
In this work, two approaches to realize a finite impulse response (FIR) filter using residue
number system (RNS) are proposed. The proposed implementations take advantage of shift …

An efficient block-based architecture for reconfigurable fir filter using partial-product method

PC Shrivastava, P Kumar, M Tiwari… - Circuits, Systems, and …, 2022 - Springer
Multipliers are the most demanding component of any filter. They not only dominate most of
the chip area but also contribute to most of the computational delay. An efficient realization …

Efficient FPGA based architecture for high‐order FIR filtering using simultaneous DSP and LUT reduced utilization

M Maamoun, A Hassani, S Dahmani… - IET Circuits, Devices …, 2021 - Wiley Online Library
This paper proposes an efficient high‐order finite impulse response (FIR) filter structure for
field programmable gate array (FPGA)‐based applications with simultaneous digital signal …

Low power and area efficient reconfigurable FIR filter implementation in FPGA

K Gunasekaran, M Manikandan - … International Conference on …, 2013 - ieeexplore.ieee.org
This paper presents an architectural approach to the design of low power and area efficient
Reconfigurable finite impulse response (FIR) filter. FIR digital filters are used in DSP by the …

High performance reconfigurable FIR filter architecture using optimized multiplier

JL Mazher Iqbal, S Varadarajan - Circuits, Systems, and Signal …, 2013 - Springer
In mobile communication systems and multimedia applications, need for efficient
reconfigurable digital finite impulse response (FIR) filters has been increasing tremendously …

FPGA implementation of high speed-low energy RNS based reconfigurable-FIR filter for cognitive radio applications

CS Murthy, K Sridevi - WSEAS Transactions on Systems and Control, 2021 - wseas.com
The Finite impulse response (FIR) filter is prominently employed in many digital signal
processing (DSP) systems for various applications. In this paper, we present a high …