Xilinx Zynq-7000 EPP: An extensible processing platform family

V Rajagopalan, V Boppana, S Dutta… - 2011 IEEE Hot Chips …, 2011 - ieeexplore.ieee.org
This article consists of a collection of slides from the author's conference presentation on the
special features, system design, processing capabilities, and targeted markets for Xilinz's …

Lightweight virtual memory support for many-core accelerators in heterogeneous embedded SoCs

P Vogel, A Marongiu, L Benini - 2015 International Conference …, 2015 - ieeexplore.ieee.org
While high-end heterogeneous systems are increasingly supporting heterogeneous uniform
memory access (hUMA) as envisioned by the Heterogeneous System Architecture (HSA) …

P2012: Building an ecosystem for a scalable, modular and high-efficiency embedded computing accelerator

L Benini, E Flamand, D Fuin… - … Design, Automation & …, 2012 - ieeexplore.ieee.org
P2012 is an area-and power-efficient many-core computing fabric based on multiple
globally asynchronous, locally synchronous (GALS) clusters supporting aggressive fine …

FUSE: Front-end user framework for O/S abstraction of hardware accelerators

A Ismail, L Shannon - 2011 IEEE 19th annual international …, 2011 - ieeexplore.ieee.org
SoCs can be implemented on a single FPGA, offering designers a unique opportunity for
Embedded Systems. Instead of defining a fixed architecture early in the design process, the …

The CM-2X: a hybrid CM-2/Xilinx prototype

SA Cuccaro, CF Reese - … IEEE Workshop on FPGAs for Custom …, 1993 - ieeexplore.ieee.org
This paper describes the CM-2X prototype. This one-of-a-kind machine is the result of a
Supercomputing Research Center/Thinking Machines Corporation joint effort to examine the …

[PDF][PDF] Partial reconfiguration of a hardware accelerator on zynq-7000 all programmable soc devices

C Kohn - Xilinx, XAPP1159 (v1. 0), 2013 - users.ece.utexas.edu
Xilinx Partial Reconfiguration of a Hardware Accelerator on Zynq-7000 All Programmable SoC
Devices (XAPP1159) Page 1 XAPP1159 (v1.0) January 21, 2013 www.xilinx.com 1 © Copyright …

5.4 Ivytown: A 22nm 15-core enterprise Xeon® processor family

S Rusu, H Muljono, D Ayers, S Tam… - … Solid-State Circuits …, 2014 - ieeexplore.ieee.org
The next-generation enterprise Xeon® server processor has 15 dual-threaded 64b Ivybridge
cores [1] and 37.5 MB shared L3 cache. The system interface includes two on-chip memory …

A project-based embedded systems design course using a reconfigurable SoC platform

D Roggow, P Uhing, P Jones… - 2015 IEEE International …, 2015 - ieeexplore.ieee.org
Embedded systems are becoming increasingly complex, as typical system components,
such as sensors and other specialized processors, are blended together with more …

The xilinx design language (xdl): Tutorial and use cases

C Beckhoff, D Koch, J Torresen - 6th International Workshop on …, 2011 - ieeexplore.ieee.org
With the Xilinx Design Language (XDL), the FPGA vendor Xilinx offers a very powerful
interface that provides access to virtually all features of their devices. This includes on one …

[图书][B] The Zynq book: embedded processing with the ARM Cortex-A9 on the Xilinx Zynq-7000 all programmable SoC

LH Crockett, RA Elliot, MA Enderwitz, RW Stewart - 2014 - dl.acm.org
This book is about the Zynq-7000 All Programmable System on Chip, the family of devices
from Xilinx that combines an application-grade ARM Cortex-A9 processor with traditional …