Standard cell-based ultra-compact DACs in 40-nm CMOS
In this paper, very compact, standard cell-based Digital-to-Analog converters (DACs) based
on the Dyadic Digital Pulse Modulation (DDPM) are presented. As fundamental contribution …
on the Dyadic Digital Pulse Modulation (DDPM) are presented. As fundamental contribution …
A 16b 6GS/s Nyquist DAC with IMD<-90dBc up to 1.9 GHz in 16nm CMOS
CH Lin, KLJ Wong, TY Kim, GR Xie… - … Solid-State Circuits …, 2018 - ieeexplore.ieee.org
Advanced communication systems require DACs with high linearity over a wide bandwidth
while consuming low power and small area [1]-[6]. In this work, a 16b 6GS/s Nyquist current …
while consuming low power and small area [1]-[6]. In this work, a 16b 6GS/s Nyquist current …
11.7 A 240mW 16b 3.2 GS/s DAC in 65nm CMOS with<-80dBc IM3 up to 600MHz
H Van de Vel, J Briaire, C Bastiaansen… - … Solid-State Circuits …, 2014 - ieeexplore.ieee.org
Advanced wireless cellular infrastructure systems require DACs with high spectral purity
over a wide bandwidth and which are fit for integration of multiple transmit channels with …
over a wide bandwidth and which are fit for integration of multiple transmit channels with …
A 14 bit 200 MS/s DAC with SFDR> 78 dBc, IM3<-83 dBc and NSD<-163 dBm/Hz across the whole nyquist band enabled by dynamic-mismatch mapping
Y Tang, J Briaire, K Doris… - IEEE Journal of Solid …, 2011 - ieeexplore.ieee.org
This paper presents a 14 bit 200 MS/s current-steering DAC with a novel digital calibration
technique called dynamic-mismatch mapping (DMM). By optimizing the switching sequence …
technique called dynamic-mismatch mapping (DMM). By optimizing the switching sequence …
Fully synthesizable low-area analogue-to-digital converters with minimal design effort based on the dyadic digital pulse modulation
In this paper, fully-synthesizable Successive Approximation Register (SAR) Analog-to-
Digital Converters (ADCs) suitable for low-cost integrated systems are proposed both for …
Digital Converters (ADCs) suitable for low-cost integrated systems are proposed both for …
A 0.07-mm2 162-mW DAC Achieving >65 dBc SFDR and < −70 dBc IM3 at 10 GS/s With Output Impedance Compensation and Concentric Parallelogram Routing
HY Huang, TH Kuo - IEEE journal of solid-state circuits, 2020 - ieeexplore.ieee.org
A digital-to-analog converter (DAC) with small-size non-cascoded current cells is proposed
to achieve small area, low-power consumption, and high linearity over a wide bandwidth. An …
to achieve small area, low-power consumption, and high linearity over a wide bandwidth. An …
A 56GS/s 6b DAC in 65nm CMOS with 256× 6b memory
YM Greshishchev, D Pollex, SC Wang… - … Solid-State Circuits …, 2011 - ieeexplore.ieee.org
This paper demonstrates more than one order of magnitude improvement in 6b CMOS DAC
design with a test circuit operating at 56Gs/s, achieving SFDR>; 30dBc and EI\IOB>; 4.3 b up …
design with a test circuit operating at 56Gs/s, achieving SFDR>; 30dBc and EI\IOB>; 4.3 b up …
A 6.5–12.5-Gb/s half-rate single-loop all-digital referenceless CDR in 28-nm CMOS
C Yu, E Sa, S Jin, H Park, J Shin… - IEEE Journal of Solid …, 2020 - ieeexplore.ieee.org
This article presents a novel method for frequency tracking based on an extended bang-
bang phase detector (XBBPD) in a referenceless clock and data recovery (CDR) circuit. The …
bang phase detector (XBBPD) in a referenceless clock and data recovery (CDR) circuit. The …
A 14 b 100 Msample/s CMOS DAC designed for spectral performance
AR Bugeja, BS Song, PL Rakers… - 1999 IEEE International …, 1999 - ieeexplore.ieee.org
At 60 MSample/s, DAC SFDR is 80 dB for 5.1 MHz input signals and is down only to 75 dB
for 25.5 MHz input signals. Previous DACs specified for operation at this speed and …
for 25.5 MHz input signals. Previous DACs specified for operation at this speed and …
Dickson-charge-pump-based voltage-to-time conversion for time-based ADCs in 28-nm CMOS
A Esmailiyan, J Du, T Siriburanon… - IEEE Open Journal …, 2020 - ieeexplore.ieee.org
This article demonstrates a digitally friendly time-based analog-to-digital converter (ADC)
exploiting Dickson charge-pump (CP) as part of a voltage-to-time conversion (VTC) …
exploiting Dickson charge-pump (CP) as part of a voltage-to-time conversion (VTC) …