For the next technological generations of integrated circuits, the traditional challenges faced
by etch plasmas (profile control, selectivity, critical dimensions, uniformity, defects,…) …

BACKGROUND The semiconductor integrated circuit (IC) industry has experienced
exponential growth. Technological advances in IC materials and design, and nanometer …

The etching of sub-100-nm porous dielectric trenches has been investigated using an
organic mask. The etching process that is performed in an oxide etcher is composed of three …

The use of a metallic hard mask approach for porous dielectric film integration implies for
patterning processes, different difficulties like dimensional control, bottom line roughness …

This study focuses on the etching characteristics of a TiN hard mask in terms of etch rate and
faceting when using a dielectric etch process. The etching experiments have been …

Metallic hard mask architecture becomes an integration of choice for an advanced back end
of the line interconnect technology node. However, one of the main integration issues is the …

Deep and narrow anisotropic etching of silicon structures has been investigated in a low-
pressure high density plasma reactor working with a cryogenic chuck. We have previously …

The recent development of a high-aspect ratio Si etch (HARSE) process has enabled the
fabrication of a variety of Si structures where deep trench etching is necessary. The HARSE …

A cryogenic etching method with SF 6/O 2 chemistry plasma in an Alcatel inductively
coupled plasma reactor is used to achieve deep trenches with high aspect ratio …

A silicon substrate, masked with oxide lines with a spacing of 1 μ m⁠, was etched using a
gas-chopping process designed to enhance mask selectivity and produce a highly …