Brloop: Constructing balanced retimed loop to architect stt-ram-based hybrid cache for vliw processors

K Qiu, Y Zhu, Y Xu, Q Huo, CJ Xue - Microelectronics Journal, 2019 - Elsevier
The new emerging non-volatile memory technology of Spin Torque Transfer RAM (STT-
RAM) has been proposed as a replacement for SRAM based cache. Recently its commercial …

Balanced loop retiming to effectively architect STT-RAM-based hybrid cache for VLIW processors

K Qiu, W Zhang, X Wu, X Zhu, J Wang, Y Xu… - Proceedings of the 31st …, 2016 - dl.acm.org
Loop retiming has been extensively studied to maximize instruction-level parallelism (ILP) of
multiple function units by rearranging the dependence delays in a uniform loop. Recently …

Architecture and data migration methodology for L1 cache design with hybrid SRAM and volatile STT-RAM configuration

WK Cheng, YH Ciou, PY Shen - Microprocessors and Microsystems, 2016 - Elsevier
Abstract Spin-Transfer Torque RAM (STT-RAM) has the advantages of circuit density and
ignorable leakage power. However, it suffers from the bad write latency and poor write …

A selective read-before-write scheme for energy-aware spin torque transfer RAM (STT-RAM) cache design

T Zhang, T Chen, J Wu, Y Qu - Journal of Circuits, Systems and …, 2013 - World Scientific
Due to its low leakage power and high density, spin torque transfer RAM (STT-RAM) has
become a good candidate for future on-chip cache. However, STT-RAM suffers from higher …

A data migration approach for L1 cache design with SRAM and volatile STT-RAM

WK Cheng, YH Ciou - ICS 2014, 2015 - books.google.com
Spin-Transfer Torque RAM (STT-RAM) has the advantages of circuit density and ignorable
leakage power. However, it suffers from the bad write latency and poor write power …

CWC: A companion write cache for energy-aware multi-level spin-transfer torque RAM cache design

T Zhang, J Zhu, J Fu, T Chen - Journal of Circuits, Systems and …, 2015 - World Scientific
Due to its large leakage power and low density, the conventional SARM becomes less
appealing to implement the large on-chip cache due to energy issue. Emerging non-volatile …

A restore-free mode for MLC STT-RAM caches

MA Qureshi, H Kim, S Kim - IEEE Transactions on Very Large …, 2019 - ieeexplore.ieee.org
Spin-transfer torque RAM (STT-RAM) caches are foreseen to replace traditional static RAM
caches because of their nonvolatile nature and high density. Multilevel cell (MLC) STT …

Mirrorcache: An energy-efficient relaxed retention l1 sttram cache

K Kuan, T Adegbija - Proceedings of the 2019 on Great Lakes …, 2019 - dl.acm.org
Spin-Transfer Torque RAM (STTRAM) is a promising alternative to SRAMs in on-chip
caches, due to several advantages, including non-volatility, low leakage, high integration …

Feedback Learning Based Dead Write Termination for Energy Efficient STT‐RAM Caches

F Shen, Y He, J Zhang, N Jiang, Q Li… - Chinese Journal of …, 2017 - Wiley Online Library
Spin‐torque transfer RAM (STT‐RAM) is a promising candidate to replace SRAM for larger
Last level cache (LLC). However, it has long write latency and high write energy which …

Compiler-assisted refresh minimization for volatile STT-RAM cache

Q Li, Y He, J Li, L Shi, Y Chen… - IEEE Transactions on …, 2014 - ieeexplore.ieee.org
Spin-transfer torque RAM (STT-RAM) has been proposed to build on-chip caches because
of its attractive features such as high storage density and ultra low leakage power. However …