Analytical Performance Modeling of LECΔ Networkon-Chip Architecture

S Gautam, A Samad, M sarosh Umar - NeuroQuantology, 2022 - search.proquest.com
This paper targets the performance evaluation of different NoC based interconnection
networks which are essentially considered as a rational way to connect huge nodes of …

Survey of network on chip architectures

MAJ Sethi, FA Hussin, NH Hamid - Science International, 2015 - scholars.utp.edu.my
Network on Chip (NoC) is a communication paradigm for on-chip communication. It has
replaced the traditional bus and crossbar interconnection as it has higher bandwidth …

[PDF][PDF] DL (2m): A New Scalable Interconnection Network for System-on-Chip.

Y Liu, J Han, H Du - J. Comput., 2009 - Citeseer
With the feature size of semiconductor technology reducing and intellectual properties (IP)
cores increasing, on chip communication architectures have a great influence on the …

An interconnection architecture for network-on-chip systems

S Suboh, M Bakhouya, J Gaber… - Telecommunication …, 2008 - Springer
Abstract Network on Chip (NoC) is a discipline research path that primarily addresses the
global communication in System on Chip (SoC). It is inspired and uses the same routing and …

[PDF][PDF] Review of different topologies for Noc architecture using NS2

K Pandey, MA Gaikwad - 2018 - academia.edu
Network-on-chip (NoC) is a packet switched onchip communication network designed using
layered methodology routes packets. NoCs use packets to route data from the source to the …

[PDF][PDF] MinRoot and CMesh: Interconnection architectures for network-on-chip systems

MAJ Jamali, A Khademzadeh - International Journal of Electronics …, 2009 - researchgate.net
Chip is highly dependent on the efficiency of its interconnection network, which is
constructed from routers and channels (the routers move data across the channels between …

[PDF][PDF] A comprehensive evaluation of direct and indirect network-on-chip topologies

M Baboli, NS Husin, MN Marsono - Proceedings of the 2014 …, 2014 - researchgate.net
Over the last few years, there has been dramatic need for developing multi-processors with
higher processing capability with area constraint. The interconnect topology for the …

[PDF][PDF] Network-on-chip (NoC) topologies and performance: a review

J Chen, C Li, P Gillard - Proceedings of the 2011 Newfoundland …, 2011 - tarjomegostar.com
With the development of integration technology, System-on-Chip (SoC), composed of
heterogeneous cores on a single chip, has entered the billion-transistor era. As the …

Design and Implementation of various topologies for Networks on Chip and its performance evolution

S Gugulothu, MD Chawhan - 2014 International Conference on …, 2014 - ieeexplore.ieee.org
The density of integration in a single chip has progressed by use of the deep submicron of
VLSI design rule. Systems on a chip (for short, SoCs), ie, several functional cores being …

[PDF][PDF] Simulation and performance evaluation for networks on chip

YR Sun - Mémoire de Master, Department of Microelectronics …, 2001 - Citeseer
Abstract The current manufacturing technology, 0.15 μm can integrate hundreds of millions
of transistors, and the integration density with increase by Moore's law that is the number of …