A low power and low in‐band phase noise W‐band frequency synthesizer in 65 nm CMOS
ABSTRACT A fully integrated 79 to 87 GHz frequency synthesizer is proposed, which
combines a W‐band push–push× 4 frequency multiplier and a K‐band divider‐less phase …
combines a W‐band push–push× 4 frequency multiplier and a K‐band divider‐less phase …
A W-band divider-less cascading frequency synthesizer with push-push× 4 frequency multiplier and sampling PLL in 65nm CMOS
A fully integrated 79-to-87GHz cascading frequency synthesizer, which combines a W-band
push-push× 4 frequency multiplier and a K-band divider-less fundamental PLL with …
push-push× 4 frequency multiplier and a K-band divider-less fundamental PLL with …
D-band frequency synthesis using a U-band PLL and frequency tripler in 65nm CMOS technology
This paper presents a digitally controlled frequency synthesizer in 65nm CMOS technology
for D-band transceiver applications. The synthesizer uses a low frequency U Band (44–48 …
for D-band transceiver applications. The synthesizer uses a low frequency U Band (44–48 …
A miniature frequency synthesizer module in W‐band
MZ Ruimin, XW Lin - Microwave and Optical Technology …, 2010 - Wiley Online Library
This article is dedicated to the research on a miniaturized W‐band multiplied phase‐locked
frequency synthesizer. This module adopts microwave frequency synthesizer and …
frequency synthesizer. This module adopts microwave frequency synthesizer and …
A fully-differential phase-locked loop frequency synthesizer for 60-GHz wireless communication
L Kuang, B Chi, L Chen, W Jia… - Journal of …, 2014 - iopscience.iop.org
A 40-GHz phase-locked loop (PLL) frequency synthesizer for 60-GHz wireless
communication applications is presented. The electrical characteristics of the passive …
communication applications is presented. The electrical characteristics of the passive …
An ultra low-power CMOS frequency synthesizer for low data-rate sub-GHz applications
CM Ippolito, A Italia, G Palmisano - 6th Conference on Ph. D …, 2010 - ieeexplore.ieee.org
An ultra low-power frequency synthesizer for sub-GHz applications was designed and
implemented in a 90-nm CMOS technology. Based on an integer-N phase-locked loop …
implemented in a 90-nm CMOS technology. Based on an integer-N phase-locked loop …
A fully integrated 0.27-THz injection-locked frequency synthesizer with frequency-tracking loop in 65-nm CMOS
A fully integrated sub-terahertz (sub-THz) frequency synthesizer is proposed cascading a
radio frequency subsampling phase-locked loop (SS-PLL) with millimeter-wave injection …
radio frequency subsampling phase-locked loop (SS-PLL) with millimeter-wave injection …
A Ku-Band Frequency Synthesizer in 0.18-m CMOS Technology
YH Peng, LH Lu - IEEE microwave and wireless components …, 2007 - ieeexplore.ieee.org
This letter presents a fully integrated frequency synthesizer implemented in a 0.18-mum
foundry CMOS process. By employing a modified differential Colpitts voltage controlled …
foundry CMOS process. By employing a modified differential Colpitts voltage controlled …
A monolithic sub-sampling PLL based 6–18 GHz frequency synthesizer for C, X, Ku band communication
H Zhou, N Zhu, W Li, Z Zhou, N Li… - IEICE Transactions on …, 2015 - search.ieice.org
A monolithic frequency synthesizer with wide tuning range, low phase noise and spurs was
realized in 0.13 μm CMOS technology. It consists of an analog PLL, a harmonic-rejection …
realized in 0.13 μm CMOS technology. It consists of an analog PLL, a harmonic-rejection …
A 433/2400 MHz dual-band frequency synthesizer with glitch-free phase-interpolated frequency divider and hybrid post-synthesizer
X Tang, X Zhao, A Hu, D Liu, Z Jin - Microelectronics Journal, 2021 - Elsevier
A three-stage low phase noise cascaded phase locked loop (PLL) with reference quadrupler
and phase-interpolated (PI) frequency divider is presented in this paper. The first stage …
and phase-interpolated (PI) frequency divider is presented in this paper. The first stage …