A fully integrated low phase noise, fast locking, 31 to 34.9 GHz dual-loop PLL
X Gai, A Trasser, H Schumacher - 2011 6th European …, 2011 - ieeexplore.ieee.org
A fully integrated dual loop PLL with ultra-low phase noise and fast lock time is presented.
The topology combines a frequency acquisition and a phase-locked hold loop. The phase …
The topology combines a frequency acquisition and a phase-locked hold loop. The phase …
A 35 GHz dual-loop PLL with low phase noise and fast lock for millimeter wave applications
X Gai, S Chartier, A Trasser… - 2011 IEEE MTT-S …, 2011 - ieeexplore.ieee.org
A fully integrated dual-loop PLL for mm-wave applications is presented. The design includes
a phase locked hold loop and a frequency acquisition loop; by using two types of phase …
a phase locked hold loop and a frequency acquisition loop; by using two types of phase …
A 5GHz 0.18-μm CMOS technology PLL with a symmetry PFD
C Yingmei, W Zhigong, Z Li - 2008 International Conference on Microwave …, 2008 - infona.pl
A fast-locking low-jitter phase-locked loop (PLL) with a simple phase-frequency detector has
been proposed. The phase-frequency detector is composed of only two XOR gates. It can …
been proposed. The phase-frequency detector is composed of only two XOR gates. It can …
A 5GHz 0.18-μm CMOS technology PLL with a symmetry PFD
Y Chen, Z Wang, L Zhang - 2008 International Conference on …, 2008 - ieeexplore.ieee.org
A fast-locking low-jitter phase-locked loop (PLL) with a simple phase-frequency detector has
been proposed. The phase-frequency detector is composed of only two XOR gates. It can …
been proposed. The phase-frequency detector is composed of only two XOR gates. It can …
A 220-225.9 GHz InP HBT Single-Chip PLL
We present a 220 GHz fundamental PLL, based on a 220 GHz VCO, 2: 1 dynamic frequency
divider, fifth-order sub-harmonic phase detector, active loop filter, and output amplifier …
divider, fifth-order sub-harmonic phase detector, active loop filter, and output amplifier …
A 300 GHz PLL in an InP HBT technology
We present a 300 GHz fundamental PLL, based on a 300 GHz VCO, 2: 1 dynamic frequency
divider, fifth-order sub-harmonic phase detector, and active loop filter, fabricated in an InP …
divider, fifth-order sub-harmonic phase detector, and active loop filter, fabricated in an InP …
A 64–84-GHz PLL with low phase noise in an 80-GHz SiGe HBT technology
G Liu, A Trasser, H Schumacher - IEEE Transactions on …, 2012 - ieeexplore.ieee.org
This paper presents a 64-84-GHz phase-locked loop (PLL) realized in a low-cost 80-GHz
HBT technology. The circuit consists of a wide tuning-range voltage-controlled oscillator, a …
HBT technology. The circuit consists of a wide tuning-range voltage-controlled oscillator, a …
A low noise multi-PFD PLL with timing shift circuit
K Tsutsumi, Y Takahashi, M Komaki… - 2012 IEEE/MTT-S …, 2012 - ieeexplore.ieee.org
A low noise multi-PFD PLL with timing shift circuit is presented. It utilize parallel circuit
configuration to improve SNR of the circuit. To enhance the effect of reducing noise, timing …
configuration to improve SNR of the circuit. To enhance the effect of reducing noise, timing …
A PLL with ultra low phase noise for millimeter wave applications
X Gai, G Liu, S Chartier, A Trasser… - The 40th European …, 2010 - ieeexplore.ieee.org
An ultra low noise phase locked loop (PLL) for millimeter wave applications is presented.
The complete design includes a mixer type phase detector, a divide-by-32 frequency divider …
The complete design includes a mixer type phase detector, a divide-by-32 frequency divider …
The 10 GHz wide tuning and low phase-noise PLL chip design
JF Huang, CC Mao, RY Liu - 2011 IEEE International …, 2011 - ieeexplore.ieee.org
An integer-N phase-locked loop (PLL) operating at 10 GHz is designed and fabricated in
TSMC 0.18-um CMOS technology. The proposed PLL with a LC-tank voltage-controlled …
TSMC 0.18-um CMOS technology. The proposed PLL with a LC-tank voltage-controlled …