Efficient and robust spike-driven deep convolutional neural networks based on NOR flash computing array

Y Xiang, P Huang, R Han, C Li, K Wang… - … on Electron Devices, 2020 - ieeexplore.ieee.org
In this article, we propose an efficient and robust spike-driven convolutional neural network
(SCNN) based on the NOR flash computing array (NFCA), which is mapped by the …

Analog deep neural network based on NOR flash computing array for high speed/energy efficiency computation

YC Xiang, P Huang, Z Zhou, RZ Han… - … on Circuits and …, 2019 - ieeexplore.ieee.org
In this paper, a novel hardware implementation of analog deep neural network (DNN) based
on NOR Flash Computing Array (NFCA) is presented. The approach eliminates additional …

Hardware implementation of energy efficient deep learning neural network based on nanoscale flash computing array

Y Xiang, P Huang, R Han, Z Zhou… - Advanced Materials …, 2019 - Wiley Online Library
Deep learning neural network (DNN) can provide efficient approaches to process the
increasing unstructured data, such as images, audio, and video. To improve the computing …

A novel convolution computing paradigm based on NOR flash array with high computing speed and energy efficiency

R Han, P Huang, Y Xiang, C Liu, Z Dong… - … on Circuits and …, 2019 - ieeexplore.ieee.org
Convolution is one of the key operations in signal processing and machine learning
applications. In this paper, we propose a novel convolution computing paradigm based on …

Flash memory array for efficient implementation of deep neural networks

R Han, Y Xiang, P Huang, Y Shan… - Advanced Intelligent …, 2021 - Wiley Online Library
The advancement of artificial intelligence applications is promoted by developing deep
neural networks (DNNs) with increasing sizes and putting forward higher computing power …

A 3D NAND flash ready 8-bit convolutional neural network core demonstrated in a standard logic process

M Kim, M Liu, L Everson, G Park, Y Jeon… - 2019 IEEE …, 2019 - ieeexplore.ieee.org
A convolutional neural network (CNN) core that can be readily mapped to a 3D NAND flash
array was demonstrated in a standard 65nm CMOS process. Logic-compatible embedded …

Flash-based computing in-memory scheme for IOT

JF Kang, P Huang, RZ Han, YC Xiang… - 2019 IEEE 13th …, 2019 - ieeexplore.ieee.org
A novel flash-based computing in-memory scheme is presented to accelerate the multiply-
accumulate (MAC) operation. Based on the novel scheme the hardware implementation and …

Optimized operation scheme of flash-memory-based neural network online training with ultra-high endurance

Y Feng, Z Sun, Y Qi, X Zhan, J Zhang… - Journal of …, 2024 - iopscience.iop.org
With the rapid development of machine learning, the demand for high-efficient computing
becomes more and more urgent. To break the bottleneck of the traditional Von Neumann …

Layer-by-layer adaptively optimized ECC of NAND flash-based SSD storing convolutional neural network weight for scene recognition

K Mizushina, T Nakamura, Y Deguchi… - … on Circuits and …, 2018 - ieeexplore.ieee.org
Layer-by-layer Adaptively Optimized Error Correcting Code (ECC) is proposed to improve
the reliability of triple-level cell (TLC) NAND flash-based SSD for the scene recognition …

[HTML][HTML] MONETA: A processing-in-memory-based hardware platform for the hybrid convolutional spiking neural network with online learning

D Kim, B Chakraborty, X She, E Lee, B Kang… - Frontiers in …, 2022 - frontiersin.org
We present a processing-in-memory (PIM)-based hardware platform, referred to as
MONETA, for on-chip acceleration of inference and learning in hybrid convolutional spiking …