A Ka-band stacked power amplifier with 24.8-dBm output power and 24.3% PAE in 65-nm CMOS technology

Y Chang, BZ Lu, Y Wang… - 2019 IEEE MTT-S …, 2019 - ieeexplore.ieee.org
This paper presents a fully integrated one-stage three-stack Ka-band power amplifier (PA)
with neutralization technique in 65-nm CMOS process for 5G applications. A transformer …

Ka-Band 3-Stack Power Amplifier with 18.8 dBm Psat and 23.4 % PAE Using 22nm CMOS FDSOI Technology

JP Aikio, M Hietanen, N Tervo… - 2019 IEEE Topical …, 2019 - ieeexplore.ieee.org
This paper presents a fully integrated, three-stack power amplifier for 5G wireless systems,
designed and fabricated using 22nm CMOS FDSOI technology. The frequency of operation …

A -Band Dual-Mode Power Amplifier in 65-nm CMOS Technology

SH Chang, CN Chen, H Wang - IEEE Microwave and Wireless …, 2018 - ieeexplore.ieee.org
In this letter, a Ka-band dual-mode power amplifier with a new topology is fabricated in 65-
nm standard CMOS. The PA with the switched capacitor to modulate the output impedance …

A 54–68 GHz power amplifier with improved linearity and efficiency in 40 nm CMOS

H Mosalam, W Xiao, X Gui, D Li… - IEEE Transactions on …, 2021 - ieeexplore.ieee.org
This brief presents a 54–68 GHz two-stage power amplifier (PA) with linearity and efficiency
enhancement in a 40 nm CMOS process. The first stage adopts a current reuse cascaded …

A high-efficiency 5G K/Ka-band stacked power amplifier in 45nm CMOS SOI process supporting 9Gb/s 64-QAM modulation with 22.4% average PAE

C Li, M Wang, T Chi, A Kumar… - … on Wireless and …, 2017 - ieeexplore.ieee.org
This paper presents a 3-FET stacked K/Ka-band class-AB power amplifier (PA) implemented
in the GLOBALFOUNDRIES 45nm SOI process that is particularly optimized for future high …

A 19.1% PAE, 22.4-dBm 53-GHz parallel power combining power amplifier with stacked-FET techniques in 90-nm CMOS

WC Sun, CN Kuo - 2019 IEEE MTT-S International Microwave …, 2019 - ieeexplore.ieee.org
A two-stage fully integrated 53-GHz stacked-FET power amplifier (PA) is implemented in 90-
nm bulk CMOS. The output stage is optimized to achieve high output power while …

A Ka-band 65-nm CMOS neutralized medium power amplifier for 5G phased-array applications

C Yu, J Feng, D Zhao - 2018 IEEE MTT-S International Wireless …, 2018 - ieeexplore.ieee.org
This paper presents a Ka-band neutralized medium power amplifier (PA). The two-stage
single-path PA adopts the neutralizing capacitors to increase the stability and three types of …

A 109 GHz CMOS power amplifier with 15.2 dBm Psat and 20.3 dB gain in 65-nm CMOS technology

HS Son, JY Jang, DM Kang, HJ Lee… - IEEE Microwave and …, 2016 - ieeexplore.ieee.org
This letter presents a four-stage power amplifier (PA) with four-way transformer-based
current combining using a standard 65 nm CMOS process. Each stage consists of common …

A K-band power amplifier with 26-dBm output power and 34% PAE with novel inductance-based neutralization in 90-nm CMOS

WC Huang, JL Lin, YH Lin… - 2018 IEEE Radio …, 2018 - ieeexplore.ieee.org
A fully-integrated K-band transformer combined power amplifier (PA) with novel
neutralization technique is presented and implemented in 90-nm CMOS technology for 5G …

5G mm-wave stacked class AB power amplifier in 45 nm PD-SOI CMOS

R Ciocoveanu, R Weigel, A Hagelauer… - 2018 Asia-Pacific …, 2018 - ieeexplore.ieee.org
This paper presents a single-stage stacked Class AB power amplifier (PA) with lower
complexity for fifth-generation (5G) K/K a band front-ends that has been realized in a 45 nm …