An FPGA has an on-chip processor that reads configuration data onto the FPGA and
controls the loading of that configuration data into FPGA configuration memory cells. After …

A field programmable gate array (FPGA) is provided that can selectively accept or reject
selected software (macros). Specifically, configuration data for the FPGA is passed through a …

A programmable gate array (FPGA) comprises a CPU coupled to a configuration memory
array. Bitstream data used for configuring the configuration memory array is encoded to …

An FPGA configuration circuit including a bus interface for applying a bit stream from either a
JTAG interface or an input/output block (IOB) interface onto a bus. The bus interface parses …

US8341469B2 - Configuration device for configuring FPGA - Google Patents
US8341469B2 - Configuration device for configuring FPGA - Google Patents Configuration …

The programmable interconnect points (PIPS) associated with each tile of an FPGA are
programmed in response to configuration data values stored in an array of configuration …

A field programmable gate array (FPGA) memory system which allows the same array of
memory to contain both configurable memory and user memory. The FPGA user logic can …

A programmable logic circuit includes a non-volatile, in-circuit programmable FPGA memory
containing configuration data for programming an FPGA to perform one or more desired …

The present invention uses high-Speed devices, embedded memories, or decoders to
rapidly configure an FPGA. In accordance with one embodiment of the present invention, a …

A method of programing an FPGA to enable encoding of configuration logic block (CLB)
outputs enabling an efficient use of FPGA routing resources. The method of the present …