Ramulator: A fast and extensible DRAM simulator

Y Kim, W Yang, O Mutlu - IEEE Computer architecture letters, 2015 - ieeexplore.ieee.org
Recently, both industry and academia have proposed many different roadmaps for the future
of DRAM. Consequently, there is a growing need for an extensible DRAM simulator, which …

DRAMsim3: A cycle-accurate, thermal-capable DRAM simulator

S Li, Z Yang, D Reddy, A Srivastava… - IEEE Computer …, 2020 - ieeexplore.ieee.org
DRAM technology has developed rapidly in recent years. Several industrial solutions offer
3D packaging of DRAM and some are envisioning the integration of CPU and DRAM on the …

DRAMSim2: A cycle accurate memory system simulator

P Rosenfeld, E Cooper-Balis… - IEEE computer …, 2011 - ieeexplore.ieee.org
In this paper we present DRAMSim2, a cycle accurate memory system simulator. The goal of
DRAMSim2 is to be an accurate and publicly available DDR2/3 memory system model …

Dramsim: a memory system simulator

D Wang, B Ganesh, N Tuaycharoen, K Baynes… - ACM SIGARCH …, 2005 - dl.acm.org
As memory accesses become slower with respect to the processor and consume more
power with increasing memory size, the focus of memory performance and power …

DRAM bender: An extensible and versatile FPGA-based infrastructure to easily test state-of-the-art DRAM chips

A Olgun, H Hassan, AG Yağlıkçı… - … on Computer-Aided …, 2023 - ieeexplore.ieee.org
To understand and improve DRAM performance, reliability, security, and energy efficiency,
prior works study characteristics of commodity DRAM chips. Unfortunately, state-of-the-art …

Simulating DRAM controllers for future system architecture exploration

A Hansson, N Agarwal, A Kolli… - … Analysis of Systems …, 2014 - ieeexplore.ieee.org
Compute requirements are increasing rapidly in systems ranging from mobile devices to
servers. These, often massively parallel architectures, put increasing requirements on …

SoftMC: A flexible and practical open-source infrastructure for enabling experimental DRAM studies

H Hassan, N Vijaykumar, S Khan… - … Symposium on High …, 2017 - ieeexplore.ieee.org
DRAM is the primary technology used for main memory in modern systems. Unfortunately,
as DRAM scales down to smaller technology nodes, it faces key challenges in both data …

Nvmain 2.0: A user-friendly memory simulator to model (non-) volatile memory systems

M Poremba, T Zhang, Y Xie - IEEE Computer Architecture …, 2015 - ieeexplore.ieee.org
In this letter, a flexible memory simulator-NVMain 2.0, is introduced to help the community for
modeling not only commodity DRAMs but also emerging memory technologies, such as die …

[PDF][PDF] Usimm: the utah simulated memory module

N Chatterjee, R Balasubramonian, M Shevgoor… - University of Utah, Tech …, 2012 - Citeseer
Abstract USIMM, the Utah SImulated Memory Module, is a DRAM main memory system
simulator that is being released for use in the Memory Scheduling Championship (MSC) …

CLR-DRAM: A low-cost DRAM architecture enabling dynamic capacity-latency trade-off

H Luo, T Shahroodi, H Hassan, M Patel… - 2020 ACM/IEEE 47th …, 2020 - ieeexplore.ieee.org
DRAM is the prevalent main memory technology, but its long access latency can limit the
performance of many workloads. Although prior works provide DRAM designs that reduce …