DRAM has been the dominant technology for architecting main memory for decades. Recent
trends in multi-core system design and large-dataset applications have amplified the role of …

Ever-growing application data footprints demand faster main memory with larger capacity.
DRAM has been the technology choice for main memory due to its low latency and high …

Dynamic random-access memory (DRAM) is the building block of modern main memory
systems. DRAM cells must be periodically refreshed to prevent loss of data. These refresh …

DRAM vendors have traditionally optimized the cost-per-bit metric, often making design
decisions that incur energy penalties. A prime example is the overfetch feature in DRAM …

DRAM memory is playing an increasingly important role in the overall power profile of latest-
generation servers with multicore processors. With many power saving techniques adopted …

The widespread use of multicore processors has dramatically increased the demand on
high memory bandwidth and large memory capacity. As DRAM subsystem designs stretch to …

Several previous works have changed DRAM bank structure to reduce memory access
latency and have shown performance improvement. However, changes in the area …

This paper describes a comprehensive approach for using the memory controller to improve
DRAM energy efficiency and manage DRAM power. We make three contributions:(1) we …

DRAM latency continues to be a critical bottleneck for system performance. In this work, we
develop a low-cost mechanism, called Charge Cache, that enables faster access to recently …

Scaling DRAM below 20nm has become a major challenge due to intrinsic limitations in the
structure of a bit cell. Future DRAM chips are likely to suffer from significant variations and …