Maximizing the inner resilience of a network-on-chip through router controllers design

DR Melo, CA Zeferino, L Dilillo, EA Bezerra - Sensors, 2019 - mdpi.com
Reducing component size and increasing the operating frequency of integrated circuits
makes the Systems-on-Chip (SoCs) more susceptible to faults. Faults can cause errors, and …

An analytical channel model for emerging wireless networks-on-chip

MO Agyeman, QT Vien, T Mak - 2016 IEEE Intl Conference on …, 2016 - ieeexplore.ieee.org
Recently wireless Networks-on-Chip (WiNoCs) have been proposed to overcome the
scalability and performance limitations of traditional multi-hop wired NoC architectures …

An efficient channel model for evaluating wireless NoC architectures

MO Agyeman, QT Vien, G Hill… - … Architecture and High …, 2016 - ieeexplore.ieee.org
Wireless Networks-on-Chip (WiNoCs) have emerged to solve the scalability and
performance bottleneck of conventional wired NoC architectures. However unlike …

High performance heterogeneous multicore architectures: A study

I Hoxha, MO Agyeman - Proceedings of the 2019 3rd International …, 2019 - dl.acm.org
The significant increase in the need for high-performance and energy-efficient computing
systems has introduced heterogenous computing. However, the incorporation of different …

基于任务映射的暗硅芯片功耗预算方法

李鑫, 李智, 周巍, 吴瑞祺, 唐浩然… - 北京航空航天大学学报, 2021 - bhxb.buaa.edu.cn
暗硅系统功耗预算问题可被归类为一种NP-hard 问题, 针对其存在的提高芯片均温与降低通信
成本2 个对立优化目标, 提出了一种基于任务映射的暗硅芯片功耗预算方法. 为降低计算复杂度 …

A survey of system level power management schemes in the dark-silicon era for many-core architectures

E Ofori-Attah, X Wang… - … on Industrial Networks …, 2018 - pure.northampton.ac.uk
Abstract Power consumption in Complementary Metal Oxide Semiconductor (CMOS)
technology has escalated to a point that only a fractional part of many-core chips can be …

Interconnects architectures for many-core era using surface-wave communication

AJM Karkar - 2016 - theses.ncl.ac.uk
Networks-on-chip (NoCs) is a communication paradigm that has emerged aiming to address
on-chip communication challenges and to satisfy interconnection demands for chip …

Blog recommender based on hypergraph modeling clustering algorithm

Y Luo, J Hu, X Wei - 2013 Fourth World Congress on Software …, 2013 - ieeexplore.ieee.org
In this paper, we presents a new blog recommender based on the hyper graph modeling
clustering algorithm. The algorithm of this system is called multilevel clustering segmentation …

A Study of FPGA-Based Supercomputing Platforms

O Challabi, Z Raghad, MO Agyeman - Proceedings of the 2019 3rd …, 2019 - dl.acm.org
Field Programmable Gate Arrays (FPGAs) play a significant role in modern supercomputing
by providing benefits of hardware speed as well as programmability. Recently, there has …

A power budgeting method for dark silicon chips based on task mapping

X LI, Z LI, W ZHOU, R WU, H TANG… - 北京航空航天大学 …, 2021 - bhxb.buaa.edu.cn
The power budgeting for dark silicon systems can be regarded as a NP-hard problem. To
achieve two opposite optimization objectives of improving chip average temperature and …