TAMA: turn-aware mapping and architecture–a power-efficient network-on-chip approach
Nowadays, static power consumption in chip multiprocessor (CMP) is the most crucial
concern of chip designers. Power-gating is an effective approach to mitigate static power …
concern of chip designers. Power-gating is an effective approach to mitigate static power …
Predictions optimal routing algorithm based on artificial intelligence technique for 3D NoC systems
F Al-Obaidy, FA Mohammadi - Microsystem Technologies, 2021 - Springer
Recently, the demand for features such as shrinkable sizes, and the concurrent need to pack
increasing numbers of transistors into a single chip, have led to the utilization of hundreds of …
increasing numbers of transistors into a single chip, have led to the utilization of hundreds of …
An improved reconfiguration algorithm for handling 1-point NoC failures
In today's world, the demands for high-performance computing necessitate faster on-chip
communication. Current chips with a large number of on-chip elements need an efficient …
communication. Current chips with a large number of on-chip elements need an efficient …
Turn-aware application mapping using reinforcement learning in power gating-enabled network on chip
M Shammasi, M Baharloo, M Abdollahi… - 2022 IEEE 15th …, 2022 - ieeexplore.ieee.org
As the backbone for many-core chips, Network-on-chips (NoCs) consume a significant share
of total chip power. As a result, decreasing the power consumption in these components can …
of total chip power. As a result, decreasing the power consumption in these components can …
Network-on-Chip Turn-aware application mapping optimization using Reinforcement Learning
M Shammasi - 2022 - dspace.library.uvic.ca
In todays advanced SoCs (System-on-Chip), power efficiency is a crucial concern. As chips
get denser and more complicated, power consumption is becoming the bottleneck in further …
get denser and more complicated, power consumption is becoming the bottleneck in further …