The Network-on-Chip paradigm has been heralded as the solution to the communication
limitation that System-on-Chip poses. As we usher into the billion-transistor era, Networkon …

In recent years, both Networks-on-Chip, as an architectural solution for high-speed
interconnect, and power consumption, as a key design constraint, have continued to gain …

The choice of a network topology for a Networks-on-Chip based application significantly
impacts its power consumption. In this paper, we propose a new methodology to reduce the …

Networks-on-Chip (NoCs) address many shortcomings of traditional interconnects.
However, they consume a considerable portion of a chip's total power-particularly when the …

Mostly communication now days is done through system on chip (SoC) models so, network
on chip (NoC) architecture is most appropriate solution for better performance. However …

Integration of large number of electronic components on a single chip has resulted in
complete and complex systems on a single chip. The energy efficiency in the System-on …

The Network-on-Chip (NoC) paradigm has been herald as the solution to the
communication limitation that System-On-Chip (SoC) poses. However, power consumption …

Applying power gating on network-on-chip (NoC) as an effective static power-aware
technique could lead to a significant reduction in on-chip network performance. Since the …

Nowadays, static power consumption in chip multiprocessor (CMP) is the most crucial
concern of chip designers. Power-gating is an effective approach to mitigate static power …

NoCs have become a critical component in many-core architectures. Usually, the preferred
topology is the 2D-Mesh as it enables a tile-based layout significantly reducing the design …