On-chip power supply network optimization using multigrid-based technique
K Wang, M Marek-Sadowska - Proceedings of the 40th annual Design …, 2003 - dl.acm.org
In this paper, we present a novel multigrid-based technique for on-chip power supply
network optimization. We reduce a large-scale network to a much coarser one which can be …
network optimization. We reduce a large-scale network to a much coarser one which can be …
Using ILA testing for BIST in FPGAs
C Stroud, E Lee, S Konala… - … Test Conference 1996 …, 1996 - ieeexplore.ieee.org
We present an improved Built-In Self-Test (BIST) approach for the programmable logic
blocks (PLBs) of a Field Programmable Gate Array (FPGA), which repeatedly reconfigures …
blocks (PLBs) of a Field Programmable Gate Array (FPGA), which repeatedly reconfigures …
An efficient design-for-testability scheme for motion estimation in H. 264/AVC
TH Wu, YL Tsai, SJ Chang - 2007 International Symposium on …, 2007 - ieeexplore.ieee.org
In this paper, a complete analysis for the input combinations of balanced and unbalanced
adder trees based on C-testability conditions is presented. Based on the analysis, a simple …
adder trees based on C-testability conditions is presented. Based on the analysis, a simple …
Testing iterative logic arrays for sequential faults with a constant number of patterns
CY Su, CW Wu - IEEE transactions on computers, 1994 - ieeexplore.ieee.org
Shows that a constant number of test vectors are sufficient for fully testing a k-dimensional
ILA for sequential faults if the cell function is bijective. The authors then present an efficient …
ILA for sequential faults if the cell function is bijective. The authors then present an efficient …
A portable ATPG tool for parallel and distributed systems
The use of parallel architectures for the solution of CPU and memory critical problems in the
electronic CAD area has been limited up to now by several factors, like the lack of efficient …
electronic CAD area has been limited up to now by several factors, like the lack of efficient …
C-Testable one-dimensional ILAs with respect to path delay faults: theory and applications
T Haniotakis, Y Tsiatouhas… - Proceedings 1998 IEEE …, 1998 - ieeexplore.ieee.org
In this paper we give, for first time in the open literature, sufficient conditions so that a one-
dimensional iterative-logic-array (ILA) is C-testable taking into account the path delay fault …
dimensional iterative-logic-array (ILA) is C-testable taking into account the path delay fault …
Testing CMOS combinational iterative logic arrays for realistic faults
In this paper we give the fundamental theory for testing one or two-dimensional Iterative
Logic Arrays (ILAs) with respect to realistic faults requiring two-pattern or generally n-pattern …
Logic Arrays (ILAs) with respect to realistic faults requiring two-pattern or generally n-pattern …
Testing combinational iterative logic arrays for realistic faults
D Gizopoulos, D Nikolos… - Proceedings 13th IEEE …, 1995 - ieeexplore.ieee.org
In this paper we give the fundamental theory for testing one or two-dimensional Iterative
Logic Arrays (ILAs) with respect to realistic faults requiring two-pattern or generally n-pattern …
Logic Arrays (ILAs) with respect to realistic faults requiring two-pattern or generally n-pattern …
An efficient design-for-testability scheme for 2-D transform in H. 264 advanced video coders
In this paper, an easily design-for-testability (DfT) scheme based on C-testability conditions
is adopted to implement test syntheses of the 2-D forward, inverse and Hadamard …
is adopted to implement test syntheses of the 2-D forward, inverse and Hadamard …
Test generation for C-testable one-dimensional CMOS ILA's without observable vertical outputs
V Hert, AJ van de Goor - Proceedings The European …, 1992 - store.computer.org
Sufficient conditions for C-testability of one-dimensional CMOS iterative logic arrays without
vertical outputs are given in the paper. Stuck-open faults in a cell are detected by pairs of …
vertical outputs are given in the paper. Stuck-open faults in a cell are detected by pairs of …