Sequential fault modeling and test pattern generation for CMOS iterative logic arrays

M Psarakis, D Gizopoulos, A Paschalis… - IEEE Transactions on …, 2000 - ieeexplore.ieee.org
Iterative Logic Arrays (ILAs) are widely used in the datapath parts of digital circuits, like
general purpose microprocessors, embedded processors, and digital signal processors …

C-testable design techniques for iterative logic arrays

SK Lu, JC Wang, CW Wu - IEEE Transactions on Very Large …, 1995 - ieeexplore.ieee.org
A design-for-testability (DFT) approach for VLSI iterative logic arrays (ILA's) is proposed,
which results in a small constant number of test patterns. Our technique applies to arrays …

Testing schemes for FIR filter structures

N Mukherjee, J Rajski, J Tyszer - IEEE Transactions on …, 2001 - ieeexplore.ieee.org
This paper presents a new pseudoexhaustive test methodology for digital finite impulse
response (FIR) filters. The proposed scheme can be employed to detect any combinational …

Built-in sequential fault self-testing of array multipliers

M Psarakis, D Gizopoulos… - IEEE Transactions on …, 2005 - ieeexplore.ieee.org
Microprocessor datapath architectures operate on signed numbers usually represented in
two's-complement or sign-magnitude formats. The multiplication operation is performed by …

Enhancing testability of VLSI arrays for fast Fourier transform

SK Lu, CW Wu, SY Kuo - IEE Proceedings E (Computers and Digital …, 1993 - IET
Fast-Fourier-transform (FFT) algorithms are used in various digital signal-processing
applications, such as linear filtering, correlation analysis and spectrum analysis. With the …

Quantum Boolean circuits are 1-testable

YH Chou, IM Tsai, SY Kuo - IEEE Transactions on …, 2008 - ieeexplore.ieee.org
Recently, a systematic procedure was proposed to derive a minimum input quantum circuit
for any given classical logic with the generalized quantum Toffoli gate, which is universal in …

High-speed easily testable Galois-field inverter

CT Huang, CW Wu - … Transactions on Circuits and Systems II …, 2000 - ieeexplore.ieee.org
Galois field (GF) computation is important in applications such as error-control coding,
switching theory, and cryptography. In GF, division and inversion operations are much …

Testing iterative logic arrays for delay faults with a constant number of patterns

SK Lu, MJ Lu - Proceedings of the 4th International Symposium …, 2002 - ieeexplore.ieee.org
Iterative logic arrays (ILAs) are widely used in many applications, eg, general-purpose
processors, digital signal processors, and embedded processors. Owing to the advanced …

C-Testable one-dimensional ILAs with respect to path delay faults: theory and applications

T Haniotakis, Y Tsiatouhas… - Proceedings 1998 IEEE …, 1998 - ieeexplore.ieee.org
In this paper we give, for first time in the open literature, sufficient conditions so that a one-
dimensional iterative-logic-array (ILA) is C-testable taking into account the path delay fault …

Delay fault testing for CMOS iterative logic arrays with a constant number of patterns

SK Lu - IEICE transactions on information and systems, 2003 - search.ieice.org
Iterative Logic Arrays (ILAs) are widely used in many applications, eg, general-purpose
processors, digital signal processors, and embedded processors. Owing to the advanced …