We present an improved Built-In Self-Test (BIST) approach for the programmable logic
blocks (PLBs) of a Field Programmable Gate Array (FPGA), which repeatedly reconfigures …

We present a new approach for Field Programmable Gate Array (FPGA) testing that exploits
the reprogrammability of FPGAs to create Built-In Self-Test (BIST) logic only during off-line …

We introduce the first BIST approach for testing the programmable routing network in
FPGAs. Our method detects opens in, and shorts among, wiring segments, and also faults …

We discuss the development of Built-In Self-Test (BIST) configurations that test all of the
programmable logic and interconnect resources in the core of Xilinx 4000E, 4000XL/XLA …

This paper presents the first BIST approach for testing interconnects of SRAM-based FPGAs
using error control coding. The proposed scheme requires a total of six test configurations …

We present a Built-In Self-Test (BIST)-based diagnostic approach for the programmable
interconnect resources in Field Programmable Gate Arrays (FPGAs) that can be used for …

An application-dependent test strategy to be used by an FPGA user is presented which
requires only 3 test configurations. In this specific strategy, the interconnect is first tested by …

We describe the development of built-in self-test (BIST) for a generic SoC consisting of a
field programmable gate array (FPGA) core for application specific logic along with a …

This paper presents a new design for testing SRAM based field programmable gate arrays
(FPGAs). The new proposed method is able to test both the configurable logic blocks (CLBs) …

Abstract Field Programmable Gate Arrays (FPGAs) are becoming more difficult to test due to
their increasing complexity and density. Test methodologies for FPGAs consist of generating …