Gate sizing and buffer insertion for optimizing performance in power constrained BiCMOS circuits
KS Lowe, PG Gulak - Proceedings of 1993 International …, 1993 - ieeexplore.ieee.org
This paper presents a method for optimizing BiCMOS logic networks that exploits the fact
that such networks may use a mixture of both CMOS and BiCMOS gates. The method …
that such networks may use a mixture of both CMOS and BiCMOS gates. The method …