This paper proposes modifications to standard island-style FPGAs that provide interconnect
capable of scaling at the same rate as typical netlists, unlike traditionally tiled FPGAs. The …

An embodiment of the invention includes a system for partitioning a control-flow graph
representation into a reconfigurable portion and an instruction processor portion. Another …

Today's digital signal processing (DSP) applications use computationally complex and/or
adaptive algorithms and have stringent requirements in terms of speed, size, cost, power …

US6961841B2 - Multiprocessor computer architecture incorporating a plurality of memory
algorithm processors in the memory subsystem - Google Patents US6961841B2 …

5,892.962 A 4/1999 Cloutier 5,903,771 A 5/1999 Sgro et al. 6,021,513 A 2/2000 Beebe et
al................. 714/726 6,023,755 A 2/2000 Casselman 6,052,773 A 4/2000 DeHon et al …

One of the most flexible and modular approaches to reconfigurable systems is a bus-based
approach. In order to get realistic performance estimates of these systems, detailed …

This doctoral thesis consists of an introductory part and eight appended publications, which
deal with hardware-based reprogrammability in algorithm acceleration with a specific …

5,473.267 A 12/1995 Stansfield device is described. More particularly, clock-to-output
5,500,943 A 3/1996 Ho et al. delays, interconnects and interconnect logic delays, and …

In DRM domain, the adversary has complete control of the computing node–supervisory
privileges along with full physical as well as architectural object observational capabilities …

We are moving towards the era of pervasive computing. The embedded computing devices
are everywhere and they need to interact in many insecure ways. Verifying the integrity of …