Loop unrolling is the main compiler technique that allows reconfigurable architectures
achieve large degrees of parallelism. However, loop unrolling increases the area and can …

In this paper, we present hthreads, a unifying programming model for specifying application
threads running within a hybrid CPU/FPGA system. Threads are specified from a single …

Although many recent advances have been made in hardware synthesis techniques from
software programming languages such as C, the performance of synthesized hardware …

The Cameron Project has developed a system for compiling codes written in a high-level
language called SA-C, to FPGA-based reconfigurable computing systems. In order to exploit …

In this paper we first outline and discuss the issues of currently accepted computational
models for hybrid CPU/FPGA systems. Then, we discuss the need for researchers to …

The mapping of image processing algorithms to hardware is complicated by several
hardware constraints including limited processing time, limited access to data and limited …

This paper presents preliminary results of automated hardware generation from C code and
discusses specific challenges. The research is part of a bigger project that aims to provide a …

Abstract FPGA (Field-Programmable Gate Array)-based custom reconfigurable computing
machines have established themselves as low-cost and low-risk alternatives to ASIC …

The logic capacity of reconfigurable devices has been increased drastically in the past ten
years. However, the design productivity is increasing at a lower pace. It is desirable to have …

In this article we present the local operations in image processing based upon spatial 2D
discrete convolution. We study different implementation of such local operations. We also …