Apparatus and method for storage processing through scalable port processors

CE Beckmann, ED Mcclanahan, G Pangal - US Patent 7,237,045, 2007 - Google Patents
A system including a storage processing device with an input/output module. The
input/output module has port processors to receive and transmit network traffic. The …

Design and performance evaluation of a Programmable Packet Processing Engine (PPE) suitable for high-speed network processors units

K Vlachos, T Orphanoudakis, Y Papaeftathiou… - Microprocessors and …, 2007 - Elsevier
In this paper, we present a Programmable Packet Processing Engine suitable for deep
header processing in high-speed networking systems. The engine, which has been …

Software-based failure detection and recovery in programmable network interfaces

Y Zhou, V Lakamraju, I Koren… - IEEE Transactions on …, 2007 - ieeexplore.ieee.org
Emerging network technologies have complex network interfaces that have renewed
concerns about network reliability. In this paper, we present an effective low-overhead fault …

Combining Compression, Encryption and Fault-tolerant Coding for Distributed Storage

P Sobe, K Peter - 2007 IEEE International Parallel and …, 2007 - ieeexplore.ieee.org
Storing data in distributed systems aims to offer higher bandwidth and scalability than
storing locally. But, a couple of disadvantageous issues must be taken into account such as …

A petri net model for evaluating packet buffering strategies in a network processor

BC Girish, R Govindarajan - Fourth International Conference on …, 2007 - ieeexplore.ieee.org
Previous studies have shown that buffering packets in DRAM is a performance bottleneck. In
order to understand the impediments in accessing the DRAM, we developed a detailed Petri …

A Characterization of High-Performance Network Monitoring Systems and Workloads

S Bunga, T Wolf - … on High Performance Switching and Routing, 2007 - ieeexplore.ieee.org
Measurement and monitoring functionality is widely deployed in the present Internet
infrastructure to gather insight into the operation of the network. It is important to obtain a …

[图书][B] Architectural and compiler optimization for network processors

J Yu - 2007 - search.proquest.com
In today's capital constrained environment, routers now must support continually evolving
requirements on aggregating a range of network protocols and traffic types. To meet such …

Latency hiding in multi-threading and multi-processing of network applications

X Guo, J Dai, L Li, Z Lv… - … Conference on Parallel …, 2007 - ieeexplore.ieee.org
Network processors employ a multithreaded, chip-multiprocessing architecture to effectively
hide memory latency and deliver high performance for packet processing applications. In …

An Embedded Networking SoC for purely Ethernet MANs/WANs

T Orphanoudakis, G Kornaros… - 2007 12th IEEE …, 2007 - ieeexplore.ieee.org
Ethernet technology is lo longer used only in Local Area Networks (LANs); it is continuously
gaining momentum in the Metropolitan Area Networks (MAN s) and Wide Area Networks …

An Efficient Policy-based Packet Scheduler With Flow Cache

G Lv, X Zhang - … Workshop on High Performance Switching and …, 2007 - ieeexplore.ieee.org
To meet the requirements of parallelism, flexibility and extensibility, the multi-Processor
Elements (PEs) architecture is widely applied in modern Network Processors (NPs) to …