Using domain partitioning in wrapper design for IP cores under power constraints
TE Yu, T Yoneda, D Zhao… - 25th IEEE VLSI Test …, 2007 - ieeexplore.ieee.org
This paper presents a novel design method for power-aware test wrappers targeting
embedded cores with multiple clock domains. We show that effective partitioning of clock …
embedded cores with multiple clock domains. We show that effective partitioning of clock …