Techniques for use in accordance with application performance decomposition are provided
which take advantage of the communications protocol used to carry a transaction between …

Future many-core CMP designs that will integrate tens of processor cores on-chip will be
constrained by area and power. Area constraints make impractical the use of a bus or a …

This chapter advocates Atomic Coherence, a framework that simplifies cache coherence
protocol specification, design, and verification by decoupling race detection and race …

Multi-core architectures have emerged as the best alternative to take advantage of the
increasing number of transistors currently offered in a single die. For example, the dual-core …

Multi-core architectures also referred to as Chip Multiprocessors (CMPs) have emerged as
the dominant architecture for both desktop and high-performance systems. CMPs introduce …

Traditional coherence protocols present a set of difficult trade-offs: the reliance of snoopy
protocols on broadcast and ordered interconnects limits their scalability, while directory …

In many fields including digital image processing and artificial retina design, they always
confront a balance issue among real-time, accuracy, computing load, power consumption …

Network-on-Chip (NoC) is proposed to solve the communication bottleneck for multi-core
SoC. Performance is one of the most critical feature of the NoC. Many different approaches …