Hardware designers invest a significant design effort when implementing computationally
intensive cryptographic algorithms onto constrained embedded devices to match the …

Naturally occurring and maliciously injected faults reduce the reliability of cryptographic
hardware and may leak confidential information. We develop a concurrent error detection …

The security of communication or computational systems protected by traditional error
detecting codes rely on the assumption that the information bits of the message (output of …

A new method using polynomial residue number systems (PRNS) is introduced in this paper
to protect the Advanced Encryption Standard (AES) against faults attacks. By using PRNS …

FOX is a family of symmetric block ciphers from MediaCrypt AG that helps to secure digital
media, communications, and storage. The high-level structure of FOX is the so-called …

Field programmable gate arrays (FPGAs) are reconfigurable devices which have emerged
as an interesting trade-off between the efficiency of application-specific integrated circuits …

This paper presents a fault-tolerant architecture for AES processors in order to mitigate the
reliability issues introduced by the continued shrinking of CMOS technology. We concentrate …

In certain embodiments, a digital signal processor (DSP) has multiple arithmetic logic units
and a register module. The DSP is adapted to generate a message digest H from a mes …

A pseudo random test strategy for the AES is presented in this paper, suitable for fault
tolerant cryptographic designs. The proposed solution is capable of assessing the integrity …

The Advanced Encryption Standard (AES) is one of the most widespread encryption
techniques used by millions of users worldwide. Although AES was designed to withstand …