Flipping bits in memory without accessing them: An experimental study of DRAM disturbance errors

Y Kim, R Daly, J Kim, C Fallin, JH Lee, D Lee… - ACM SIGARCH …, 2014 - dl.acm.org
Memory isolation is a key property of a reliable and secure computing system--an access to
one memory address should not have unintended side effects on data stored in other …

Improving DRAM performance by parallelizing refreshes with accesses

KKW Chang, D Lee, Z Chishti… - 2014 IEEE 20th …, 2014 - ieeexplore.ieee.org
Modern DRAM cells are periodically refreshed to prevent data loss due to leakage.
Commodity DDR (double data rate) DRAM refreshes cells at the rank level. This degrades …

[PDF][PDF] Research problems and opportunities in memory systems

O Mutlu, L Subramanian - Supercomputing frontiers and …, 2014 - superfri.susu.ru
The memory system is a fundamental performance and energy bottleneck in almost all
computing systems. Recent system design, application, and technology trends that require …

The efficacy of error mitigation techniques for DRAM retention failures: A comparative experimental study

S Khan, D Lee, Y Kim, AR Alameldeen… - ACM SIGMETRICS …, 2014 - dl.acm.org
As DRAM cells continue to shrink, they become more susceptible to retention failures.
DRAM cells that permanently exhibit short retention times are fairly easy to identify and …

Characterizing application memory error vulnerability to optimize datacenter cost via heterogeneous-reliability memory

Y Luo, S Govindan, B Sharma… - 2014 44th Annual …, 2014 - ieeexplore.ieee.org
Memory devices represent a key component of datacenter total cost of ownership (TCO),
and techniques used to reduce errors that occur on these devices increase this cost. Existing …

Transparent hardware management of stacked dram as part of memory

J Sim, AR Alameldeen, Z Chishti… - 2014 47th Annual …, 2014 - ieeexplore.ieee.org
Recent technology advancements allow for the integration of large memory structures on-die
or as a die-stacked DRAM. Such structures provide higher bandwidth and faster access time …

The blacklisting memory scheduler: Achieving high performance and fairness at low cost

L Subramanian, D Lee, V Seshadri… - 2014 IEEE 32nd …, 2014 - ieeexplore.ieee.org
In a multicore system, applications running on different cores interfere at main memory. This
inter-application interference degrades overall system performance and unfairly slows down …

NUAT: A non-uniform access time memory controller

W Shin, J Yang, J Choi, LS Kim - 2014 IEEE 20th International …, 2014 - ieeexplore.ieee.org
With rapid development of micro-processors, off-chip memory access becomes a system
bottleneck. DRAM, a main memory in most computers, has concentrated only on capacity …

Row-buffer decoupling: A case for low-latency DRAM microarchitecture

O Seongil, YH Son, NS Kim… - 2014 ACM/IEEE 41st …, 2014 - ieeexplore.ieee.org
Modern DRAM devices for the main memory are structured to have multiple banks to satisfy
ever-increasing throughput, energy-efficiency, and capacity demands. Due to tight cost …

Microbank: Architecting through-silicon interposer-based main memory systems

YH Son, O Seongil, H Yang, D Jung… - SC'14: Proceedings …, 2014 - ieeexplore.ieee.org
Through-Silicon Interposer (TSI) has recently been proposed to provide high memory
bandwidth and improve energy efficiency of the main memory system. However, the impact …