System and method for a cache in a multi-core processor
M Vorbach - US Patent 9,086,973, 2015 - Google Patents
The invention relates to a multi-core processor system, in particular a single-package multi-
core processor system, comprising at least two processor cores, preferably at least four …
core processor system, comprising at least two processor cores, preferably at least four …
Multiple data channel memory module architecture
TM Brewer, JM Andrewartha, WD O'leary… - US Patent …, 2015 - Google Patents
The present invention is directed generally to systems and methods which provide a
memory module having multiple data channels that are independently accessible (ie, a multi …
memory module having multiple data channels that are independently accessible (ie, a multi …
Processor arrangement on a chip including data processing, memory, and interface elements
M Vorbach - US Patent 9,037,807, 2015 - Google Patents
Related US Application Data G06F II/20(2006.01)(60) Division of application No.
12/496.012, filed on Jul. 1, G06F 3/16(2006.01) 2009, now abandoned, which is a …
12/496.012, filed on Jul. 1, G06F 3/16(2006.01) 2009, now abandoned, which is a …
Logical cell array and bus system
M Vorbach, F May, D Reichardt, L Frank… - US Patent …, 2015 - Google Patents
Mar. 7, 2001 (DE).................................. 101 11 O14 A logic cell array having a number of logic
cells and a seg Jul. 24, 2001 (DE) 101 35210 mented bus system for logic cell …
cells and a seg Jul. 24, 2001 (DE) 101 35210 mented bus system for logic cell …
Heads-up-display software development tool
NG Duca, V Stamate, T Flynn, S Peterson… - US Patent …, 2015 - Google Patents
US9013494B2 - Heads-up-display software development tool - Google Patents
US9013494B2 - Heads-up-display software development tool - Google Patents Heads-up-display …
US9013494B2 - Heads-up-display software development tool - Google Patents Heads-up-display …
Methods and devices for treating and processing data
M Vorbach, V Baumgarte - US Patent 9,075,605, 2015 - Google Patents
A data processing unit having a field of clocked logic cells (PAEs) which is operable in
different configuration states and a clock preselecting means for preselecting logic cell …
different configuration states and a clock preselecting means for preselecting logic cell …