Reducing power with activity trigger analysis
J Lanik, J Legriel, E Piriou, E Viaud… - 2015 ACM/IEEE …, 2015 - ieeexplore.ieee.org
In this paper we propose and implement a methodology for power reduction in digital
circuits, closing the gap between conceptual (by designer) and local (by EDA) clock gating …
circuits, closing the gap between conceptual (by designer) and local (by EDA) clock gating …
Strategies for Performance and Quality Improvement of Hardware Verification and Synthesis Algorithms
MAMS Elbayoumi - 2015 - vtechworks.lib.vt.edu
According to Moore's law, Integrated Chips (IC) doubles its capacity every 18 months. This
causes an exponential increase of the available area, and hence, the complexity of modern …
causes an exponential increase of the available area, and hence, the complexity of modern …