A review on regional convection‐permitting climate modeling: Demonstrations, prospects, and challenges

AF Prein, W Langhans, G Fosser… - Reviews of …, 2015 - Wiley Online Library
Regional climate modeling using convection‐permitting models (CPMs; horizontal grid
spacing< 4 km) emerges as a promising framework to provide more reliable climate …

The application slowdown model: Quantifying and controlling the impact of inter-application interference at shared caches and main memory

L Subramanian, V Seshadri, A Ghosh, S Khan… - Proceedings of the 48th …, 2015 - dl.acm.org
In a multi-core system, interference at shared resources (such as caches and main memory)
slows down applications running on different cores. Accurately estimating the slowdown of …

Parallelism-aware memory interference delay analysis for COTS multicore systems

H Yun, R Pellizzon, PK Valsan - 2015 27th Euromicro …, 2015 - ieeexplore.ieee.org
In modern Commercial Off-The-Shelf (COTS) mul-ticore systems, each core can generate
many parallel memory requests at a time. The processing of these parallel requests in the …

Cache sharing and isolation tradeoffs in multicore mixed-criticality systems

M Chisholm, BC Ward, N Kim… - 2015 IEEE Real-Time …, 2015 - ieeexplore.ieee.org
In mixed-critical applications, tension exists between sharing and isolation with respect to
hardware resources: while strong isolation might be required for highly critical tasks …

Supporting differentiated services in computers via programmable architecture for resourcing-on-demand (PARD)

J Ma, X Sui, N Sun, Y Li, Z Yu, B Huang, T Xu… - Proceedings of the …, 2015 - dl.acm.org
This paper presents PARD, a programmable architecture for resourcing-on-demand that
provides a new programming interface to convey an application's high-level information like …

The main memory system: Challenges and opportunities

O Mutlu, J Meza, L Subramanian - Communications of the Korean …, 2015 - koreascience.kr
The memory system is a fundamental performance and energy bottleneck in almost all
computing systems. Recent system design, application, and technology trends that require …

[PDF][PDF] Architectural techniques to enhance DRAM scaling

Y Kim - Ph. D. dissertation, Carnegie Mellon University, 2015 - kilthub.cmu.edu
For decades, main memory has enjoyed the continuous scaling of its physical substrate:
DRAM (DynamicRandomAccessMemory). Butnow, DRAMscalinghasreachedathreshold …

MEDUSA: a predictable and high-performance DRAM controller for multicore based embedded systems

PK Valsan, H Yun - 2015 IEEE 3rd international conference on …, 2015 - ieeexplore.ieee.org
Commercial-Off-The-Shelf (COTS) DRAM controllers are optimized for high memory
throughput, but they do not provide predictable timing among memory requests from …

Rethinking memory management in modern operating system: Horizontal, vertical or random?

L Liu, Y Li, C Ding, H Yang, C Wu - IEEE Transactions on …, 2015 - ieeexplore.ieee.org
On modern multicore machines, the memory management typically combines address
interleaving in hardware and random allocation in the operating system (OS) to improve …

Improved dram timing bounds for real-time dram controllers with read/write bundling

L Ecco, R Ernst - 2015 IEEE Real-Time Systems Symposium, 2015 - ieeexplore.ieee.org
As DRAMs become faster, the penalty to reverse the direction of their data buses increases.
Yet, existing real-time memory controllers do not reorder read and write commands. Hence …